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[RISCV] Remove unncessary FP extensions from some integer only vector tests.
I'm going to do a review to make sure we are testing Zvfhmin instead of Zvfh where clang expects it to work for half types, like loads/stores. Removing unnecessary FP makes less things to review.
1 parent 785a24f commit 26766a0

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+54
-54
lines changed

‎llvm/test/CodeGen/RISCV/rvv/abs-vp.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \
2+
; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
4-
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \
4+
; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
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declare <vscale x 1 x i8> @llvm.vp.abs.nxv1i8(<vscale x 1 x i8>, i1 immarg, <vscale x 1 x i1>, i32)

‎llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
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11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \
2+
; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
4-
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \
4+
; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
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; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb,+m -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB

‎llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll

Lines changed: 2 additions & 2 deletions
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@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \
2+
; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
4-
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \
4+
; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
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; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb,+m -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB

‎llvm/test/CodeGen/RISCV/rvv/commutable.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f,+d,+zvfh,+v \
2+
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
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; RUN: -verify-machineinstrs | FileCheck %s
4-
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f,+d,+zvfh,+v \
4+
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
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; RUN: -verify-machineinstrs | FileCheck %s
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; vadd.vv

‎llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll

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11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \
2+
; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
4-
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \
4+
; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
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; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb,+m -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB

‎llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll

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11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \
2+
; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32NOM
4-
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \
4+
; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32M
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‎llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll

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11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \
2+
; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV64NOM
4-
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \
4+
; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV64M
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define signext i8 @extractelt_nxv1i8_0(<vscale x 1 x i8> %v) {

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll

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@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \
2+
; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
4-
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \
4+
; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
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declare <2 x i8> @llvm.vp.abs.v2i8(<2 x i8>, i1 immarg, <2 x i1>, i32)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll

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@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \
2+
; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
4-
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \
4+
; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
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declare <2 x i8> @llvm.vp.bitreverse.v2i8(<2 x i8>, <2 x i1>, i32)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \
2+
; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
4-
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \
4+
; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
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declare <2 x i16> @llvm.vp.bswap.v2i16(<2 x i16>, <2 x i1>, i32)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -verify-machineinstrs < %s | FileCheck %s
2+
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
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define <4 x i8> @ret_v4i8(ptr %p) {
55
; CHECK-LABEL: ret_v4i8:

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \
2+
; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \
33
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
4-
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \
4+
; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
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declare <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8>, i1 immarg, <2 x i1>, i32)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll

Lines changed: 2 additions & 2 deletions
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@@ -1,7 +1,7 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \
2+
; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \
33
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
4-
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \
4+
; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
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declare <2 x i8> @llvm.vp.ctpop.v2i8(<2 x i8>, <2 x i1>, i32)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll

Lines changed: 2 additions & 2 deletions
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \
2+
; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \
33
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
4-
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \
4+
; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
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declare <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8>, i1 immarg, <2 x i1>, i32)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll

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@@ -1,6 +1,6 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -verify-machineinstrs < %s | FileCheck %s
3-
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -verify-machineinstrs < %s | FileCheck %s
2+
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
3+
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
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define <2 x i16> @sextload_v2i1_v2i16(ptr %x) {
66
; CHECK-LABEL: sextload_v2i1_v2i16:

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll

Lines changed: 4 additions & 4 deletions
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@@ -1,9 +1,9 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
3-
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
2+
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
3+
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
44

5-
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d,+zbs -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32ZBS
6-
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d,+zbs -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64ZBS
5+
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zbs -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32ZBS
6+
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zbs -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64ZBS
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define i1 @extractelt_v1i1(ptr %x, i64 %idx) nounwind {
99
; CHECK-LABEL: extractelt_v1i1:

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-extract-subvector.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2-
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
3-
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
2+
; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
3+
; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
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define <8 x i8> @v8i8_from_v16xi8_low(<16 x i8> %a) nounwind {
66
; CHECK-LABEL: v8i8_from_v16xi8_low:

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll

Lines changed: 2 additions & 2 deletions
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@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \
2+
; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \
33
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
4-
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \
4+
; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
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declare <2 x i8> @llvm.vp.mul.nxv2i8(<2 x i8>, <2 x i8>, <2 x i1>, i32)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll

Lines changed: 2 additions & 2 deletions
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@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \
2+
; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \
33
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
4-
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \
4+
; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
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declare <2 x i8> @llvm.vp.mul.nxv2i8(<2 x i8>, <2 x i8>, <2 x i1>, i32)

‎llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll

Lines changed: 1 addition & 1 deletion
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@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \
2+
; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32d \
33
; RUN: -verify-machineinstrs < %s | FileCheck %s
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define <vscale x 1 x i8> @insertelt_nxv1i8_0(<vscale x 1 x i8> %v, i8 signext %elt) {

‎llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll

Lines changed: 1 addition & 1 deletion
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@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \
2+
; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64d \
33
; RUN: -verify-machineinstrs < %s | FileCheck %s
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define <vscale x 1 x i8> @insertelt_nxv1i8_0(<vscale x 1 x i8> %v, i8 signext %elt) {

‎llvm/test/CodeGen/RISCV/rvv/legalize-store-sdnode.ll

Lines changed: 2 additions & 2 deletions
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@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s
3-
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s
2+
; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s
3+
; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s
44

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; Check that we are able to legalize scalable-vector stores that require widening.
66

‎llvm/test/CodeGen/RISCV/rvv/mscatter-combine.ll

Lines changed: 2 additions & 2 deletions
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@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+zvfh,+v -target-abi=ilp32d \
2+
; RUN: llc -mtriple=riscv32 -mattr=+m,+v -target-abi=ilp32d \
33
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32
4-
; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+zvfh,+v -target-abi=lp64d \
4+
; RUN: llc -mtriple=riscv64 -mattr=+m,+v -target-abi=lp64d \
55
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64
66

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%struct = type { i64, i64, ptr, i32, i32, i32, [4 x i32] }

‎llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll

Lines changed: 1 addition & 1 deletion
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@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh,+m \
2+
; RUN: llc -mtriple=riscv32 -mattr=+v,+m \
33
; RUN: -regalloc=fast -verify-machineinstrs < %s | FileCheck %s
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; This test previously crashed with an error "ran out of registers during register allocation"

‎llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll

Lines changed: 1 addition & 1 deletion
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@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zfh,+zvfh \
2+
; RUN: llc -mtriple=riscv32 -mattr=+zve64x \
33
; RUN: -verify-machineinstrs < %s | FileCheck %s
44

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declare {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, ptr , i32)

‎llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll

Lines changed: 1 addition & 1 deletion
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11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+zvfh \
2+
; RUN: llc -mtriple=riscv64 -mattr=+zve64x \
33
; RUN: -verify-machineinstrs < %s | FileCheck %s
44

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declare {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, ptr , i64)

‎llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \
2+
; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \
33
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
4-
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \
4+
; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \
55
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
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declare <vscale x 1 x i8> @llvm.vp.mul.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)

‎llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll

Lines changed: 2 additions & 2 deletions
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11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \
2+
; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \
33
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
4-
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \
4+
; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \
55
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
66

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declare <vscale x 1 x i8> @llvm.vp.mul.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)

‎llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \
2+
; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \
33
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
4-
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \
4+
; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \
55
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
66

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declare <vscale x 1 x i8> @llvm.vp.mul.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)

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