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[RISCV] Rename the RVVBaseAddr ComplexPattern to just BaseAddr and use it to merge some scalar load/store patterns too.
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6 files changed

+32
-42
lines changed

6 files changed

+32
-42
lines changed

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -915,7 +915,7 @@ bool RISCVDAGToDAGISel::SelectAddrFI(SDValue Addr, SDValue &Base) {
915915
return false;
916916
}
917917

918-
bool RISCVDAGToDAGISel::SelectRVVBaseAddr(SDValue Addr, SDValue &Base) {
918+
bool RISCVDAGToDAGISel::SelectBaseAddr(SDValue Addr, SDValue &Base) {
919919
// If this is FrameIndex, select it directly. Otherwise just let it get
920920
// selected to a register independently.
921921
if (auto *FIN = dyn_cast<FrameIndexSDNode>(Addr))

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,7 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
4444
std::vector<SDValue> &OutOps) override;
4545

4646
bool SelectAddrFI(SDValue Addr, SDValue &Base);
47-
bool SelectRVVBaseAddr(SDValue Addr, SDValue &Base);
47+
bool SelectBaseAddr(SDValue Addr, SDValue &Base);
4848

4949
bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);
5050
bool selectShiftMaskXLen(SDValue N, SDValue &ShAmt) {

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

Lines changed: 7 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -298,6 +298,7 @@ def uimm6gt32 : ImmLeaf<XLenVT, [{
298298
// Addressing modes.
299299
// Necessary because a frameindex can't be matched directly in a pattern.
300300
def AddrFI : ComplexPattern<iPTR, 1, "SelectAddrFI", [frameindex], []>;
301+
def BaseAddr : ComplexPattern<iPTR, 1, "SelectBaseAddr">;
301302

302303
// Extract least significant 12 bits from an immediate value and sign extend
303304
// them.
@@ -1110,12 +1111,9 @@ def PseudoZEXT_W : Pseudo<(outs GPR:$rd), (ins GPR:$rs), [], "zext.w", "$rd, $rs
11101111
/// Loads
11111112

11121113
multiclass LdPat<PatFrag LoadOp, RVInst Inst> {
1113-
def : Pat<(LoadOp GPR:$rs1), (Inst GPR:$rs1, 0)>;
1114-
def : Pat<(LoadOp AddrFI:$rs1), (Inst AddrFI:$rs1, 0)>;
1115-
def : Pat<(LoadOp (add GPR:$rs1, simm12:$imm12)),
1116-
(Inst GPR:$rs1, simm12:$imm12)>;
1117-
def : Pat<(LoadOp (add AddrFI:$rs1, simm12:$imm12)),
1118-
(Inst AddrFI:$rs1, simm12:$imm12)>;
1114+
def : Pat<(LoadOp BaseAddr:$rs1), (Inst BaseAddr:$rs1, 0)>;
1115+
def : Pat<(LoadOp (add BaseAddr:$rs1, simm12:$imm12)),
1116+
(Inst BaseAddr:$rs1, simm12:$imm12)>;
11191117
def : Pat<(LoadOp (IsOrAdd AddrFI:$rs1, simm12:$imm12)),
11201118
(Inst AddrFI:$rs1, simm12:$imm12)>;
11211119
}
@@ -1131,12 +1129,9 @@ defm : LdPat<zextloadi16, LHU>;
11311129
/// Stores
11321130

11331131
multiclass StPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy> {
1134-
def : Pat<(StoreOp StTy:$rs2, GPR:$rs1), (Inst StTy:$rs2, GPR:$rs1, 0)>;
1135-
def : Pat<(StoreOp StTy:$rs2, AddrFI:$rs1), (Inst StTy:$rs2, AddrFI:$rs1, 0)>;
1136-
def : Pat<(StoreOp StTy:$rs2, (add GPR:$rs1, simm12:$imm12)),
1137-
(Inst StTy:$rs2, GPR:$rs1, simm12:$imm12)>;
1138-
def : Pat<(StoreOp StTy:$rs2, (add AddrFI:$rs1, simm12:$imm12)),
1139-
(Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>;
1132+
def : Pat<(StoreOp StTy:$rs2, BaseAddr:$rs1), (Inst StTy:$rs2, BaseAddr:$rs1, 0)>;
1133+
def : Pat<(StoreOp StTy:$rs2, (add BaseAddr:$rs1, simm12:$imm12)),
1134+
(Inst StTy:$rs2, BaseAddr:$rs1, simm12:$imm12)>;
11401135
def : Pat<(StoreOp StTy:$rs2, (IsOrAdd AddrFI:$rs1, simm12:$imm12)),
11411136
(Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>;
11421137
}

‎llvm/lib/Target/RISCV/RISCVInstrInfoA.td

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -62,12 +62,9 @@ multiclass AMO_rr_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr> {
6262
}
6363

6464
multiclass AtomicStPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy> {
65-
def : Pat<(StoreOp GPR:$rs1, StTy:$rs2), (Inst StTy:$rs2, GPR:$rs1, 0)>;
66-
def : Pat<(StoreOp AddrFI:$rs1, StTy:$rs2), (Inst StTy:$rs2, AddrFI:$rs1, 0)>;
67-
def : Pat<(StoreOp (add GPR:$rs1, simm12:$imm12), StTy:$rs2),
68-
(Inst StTy:$rs2, GPR:$rs1, simm12:$imm12)>;
69-
def : Pat<(StoreOp (add AddrFI:$rs1, simm12:$imm12), StTy:$rs2),
70-
(Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>;
65+
def : Pat<(StoreOp BaseAddr:$rs1, StTy:$rs2), (Inst StTy:$rs2, BaseAddr:$rs1, 0)>;
66+
def : Pat<(StoreOp (add BaseAddr:$rs1, simm12:$imm12), StTy:$rs2),
67+
(Inst StTy:$rs2, BaseAddr:$rs1, simm12:$imm12)>;
7168
def : Pat<(StoreOp (IsOrAdd AddrFI:$rs1, simm12:$imm12), StTy:$rs2),
7269
(Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>;
7370
}

‎llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Lines changed: 12 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -37,8 +37,6 @@ def SplatPat : ComplexPattern<vAny, 1, "selectVSplat", [splat_vector,
3737
def SplatPat_simm5 : ComplexPattern<vAny, 1, "selectVSplatSimm5", [splat_vector, rv32_splat_i64], [], 2>;
3838
def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimm5", [splat_vector, rv32_splat_i64], [], 2>;
3939

40-
def RVVBaseAddr : ComplexPattern<iPTR, 1, "SelectRVVBaseAddr">;
41-
4240
class SwapHelper<dag Prefix, dag A, dag B, dag Suffix, bit swap> {
4341
dag Value = !con(Prefix, !if(swap, B, A), !if(swap, A, B), Suffix);
4442
}
@@ -60,11 +58,11 @@ multiclass VPatUSLoadStoreSDNode<ValueType type,
6058
defvar load_instr = !cast<Instruction>("PseudoVLE"#sew#"_V_"#vlmul.MX);
6159
defvar store_instr = !cast<Instruction>("PseudoVSE"#sew#"_V_"#vlmul.MX);
6260
// Load
63-
def : Pat<(type (load RVVBaseAddr:$rs1)),
64-
(load_instr RVVBaseAddr:$rs1, avl, sew)>;
61+
def : Pat<(type (load BaseAddr:$rs1)),
62+
(load_instr BaseAddr:$rs1, avl, sew)>;
6563
// Store
66-
def : Pat<(store type:$rs2, RVVBaseAddr:$rs1),
67-
(store_instr reg_class:$rs2, RVVBaseAddr:$rs1, avl, sew)>;
64+
def : Pat<(store type:$rs2, BaseAddr:$rs1),
65+
(store_instr reg_class:$rs2, BaseAddr:$rs1, avl, sew)>;
6866
}
6967

7068
multiclass VPatUSLoadStoreWholeVRSDNode<LLVMType type,
@@ -84,23 +82,23 @@ multiclass VPatUSLoadStoreWholeVRSDNode<LLVMType type,
8482
!eq(vlmul.value, V_M8.value): VS8R_V);
8583

8684
// Load
87-
def : Pat<(type (load RVVBaseAddr:$rs1)),
88-
(load_instr RVVBaseAddr:$rs1)>;
85+
def : Pat<(type (load BaseAddr:$rs1)),
86+
(load_instr BaseAddr:$rs1)>;
8987
// Store
90-
def : Pat<(store type:$rs2, RVVBaseAddr:$rs1),
91-
(store_instr reg_class:$rs2, RVVBaseAddr:$rs1)>;
88+
def : Pat<(store type:$rs2, BaseAddr:$rs1),
89+
(store_instr reg_class:$rs2, BaseAddr:$rs1)>;
9290
}
9391

9492
multiclass VPatUSLoadStoreMaskSDNode<MTypeInfo m>
9593
{
9694
defvar load_instr = !cast<Instruction>("PseudoVLE1_V_"#m.BX);
9795
defvar store_instr = !cast<Instruction>("PseudoVSE1_V_"#m.BX);
9896
// Load
99-
def : Pat<(m.Mask (load RVVBaseAddr:$rs1)),
100-
(load_instr RVVBaseAddr:$rs1, m.AVL, m.SEW)>;
97+
def : Pat<(m.Mask (load BaseAddr:$rs1)),
98+
(load_instr BaseAddr:$rs1, m.AVL, m.SEW)>;
10199
// Store
102-
def : Pat<(store m.Mask:$rs2, RVVBaseAddr:$rs1),
103-
(store_instr VR:$rs2, RVVBaseAddr:$rs1, m.AVL, m.SEW)>;
100+
def : Pat<(store m.Mask:$rs2, BaseAddr:$rs1),
101+
(store_instr VR:$rs2, BaseAddr:$rs1, m.AVL, m.SEW)>;
104102
}
105103

106104
class VPatBinarySDNode_VV<SDNode vop,

‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -313,22 +313,22 @@ foreach vti = AllVectors in {
313313
defvar load_instr = !cast<Instruction>("PseudoVLE"#vti.SEW#"_V_"#vti.LMul.MX);
314314
defvar store_instr = !cast<Instruction>("PseudoVSE"#vti.SEW#"_V_"#vti.LMul.MX);
315315
// Load
316-
def : Pat<(vti.Vector (riscv_vle_vl RVVBaseAddr:$rs1, (XLenVT (VLOp GPR:$vl)))),
317-
(load_instr RVVBaseAddr:$rs1, GPR:$vl, vti.SEW)>;
316+
def : Pat<(vti.Vector (riscv_vle_vl BaseAddr:$rs1, (XLenVT (VLOp GPR:$vl)))),
317+
(load_instr BaseAddr:$rs1, GPR:$vl, vti.SEW)>;
318318
// Store
319-
def : Pat<(riscv_vse_vl (vti.Vector vti.RegClass:$rs2), RVVBaseAddr:$rs1,
319+
def : Pat<(riscv_vse_vl (vti.Vector vti.RegClass:$rs2), BaseAddr:$rs1,
320320
(XLenVT (VLOp GPR:$vl))),
321-
(store_instr vti.RegClass:$rs2, RVVBaseAddr:$rs1, GPR:$vl, vti.SEW)>;
321+
(store_instr vti.RegClass:$rs2, BaseAddr:$rs1, GPR:$vl, vti.SEW)>;
322322
}
323323

324324
foreach mti = AllMasks in {
325325
defvar load_instr = !cast<Instruction>("PseudoVLE1_V_"#mti.BX);
326326
defvar store_instr = !cast<Instruction>("PseudoVSE1_V_"#mti.BX);
327-
def : Pat<(mti.Mask (riscv_vle_vl RVVBaseAddr:$rs1, (XLenVT (VLOp GPR:$vl)))),
328-
(load_instr RVVBaseAddr:$rs1, GPR:$vl, mti.SEW)>;
329-
def : Pat<(riscv_vse_vl (mti.Mask VR:$rs2), RVVBaseAddr:$rs1,
327+
def : Pat<(mti.Mask (riscv_vle_vl BaseAddr:$rs1, (XLenVT (VLOp GPR:$vl)))),
328+
(load_instr BaseAddr:$rs1, GPR:$vl, mti.SEW)>;
329+
def : Pat<(riscv_vse_vl (mti.Mask VR:$rs2), BaseAddr:$rs1,
330330
(XLenVT (VLOp GPR:$vl))),
331-
(store_instr VR:$rs2, RVVBaseAddr:$rs1, GPR:$vl, mti.SEW)>;
331+
(store_instr VR:$rs2, BaseAddr:$rs1, GPR:$vl, mti.SEW)>;
332332
}
333333

334334
// 12.1. Vector Single-Width Integer Add and Subtract

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