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[LV] Move reduction PHI node fixup to VPlan::execute (NFC).
All information to fix-up the reduction phi nodes in the vectorized loop is available in VPlan now. This patch moves the code to do so, to make this clearer. Fixing up the loop exit value still relies on other information and remains outside of VPlan for now. Reviewed By: Ayal Differential Revision: https://reviews.llvm.org/D100113
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+21
-26
lines changed

2 files changed

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llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

Lines changed: 1 addition & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -594,8 +594,7 @@ class InnerLoopVectorizer {
594594
/// update their users.
595595
void fixFirstOrderRecurrence(VPWidenPHIRecipe *PhiR, VPTransformState &State);
596596

597-
/// Fix a reduction cross-iteration phi. This is the second phase of
598-
/// vectorizing this phi node.
597+
/// Create code for the loop exit value of the reduction.
599598
void fixReduction(VPReductionPHIRecipe *Phi, VPTransformState &State);
600599

601600
/// Clear NSW/NUW flags from reduction instructions if necessary.
@@ -4303,22 +4302,6 @@ void InnerLoopVectorizer::fixReduction(VPReductionPHIRecipe *PhiR,
43034302
// Wrap flags are in general invalid after vectorization, clear them.
43044303
clearReductionWrapFlags(RdxDesc, State);
43054304

4306-
// Fix the vector-loop phi.
4307-
4308-
// Reductions do not have to start at zero. They can start with
4309-
// any loop invariant values.
4310-
BasicBlock *VectorLoopLatch = LI->getLoopFor(LoopVectorBody)->getLoopLatch();
4311-
4312-
unsigned LastPartForNewPhi = PhiR->isOrdered() ? 1 : UF;
4313-
for (unsigned Part = 0; Part < LastPartForNewPhi; ++Part) {
4314-
Value *VecRdxPhi = State.get(PhiR->getVPSingleValue(), Part);
4315-
Value *Val = State.get(PhiR->getBackedgeValue(), Part);
4316-
if (PhiR->isOrdered())
4317-
Val = State.get(PhiR->getBackedgeValue(), UF - 1);
4318-
4319-
cast<PHINode>(VecRdxPhi)->addIncoming(Val, VectorLoopLatch);
4320-
}
4321-
43224305
// Before each round, move the insertion point right between
43234306
// the PHIs and the values we are going to write.
43244307
// This allows us to write both PHINodes and the extractelement

llvm/lib/Transforms/Vectorize/VPlan.cpp

Lines changed: 20 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -815,16 +815,25 @@ void VPlan::execute(VPTransformState *State) {
815815
for (VPBlockBase *Block : depth_first(Entry))
816816
Block->execute(State);
817817

818-
// Fix the latch value of the first-order recurrences in the vector loop. Only
819-
// a single part is generated, regardless of the UF.
818+
// Fix the latch value of reduction and first-order recurrences phis in the
819+
// vector loop.
820820
VPBasicBlock *Header = Entry->getEntryBasicBlock();
821821
for (VPRecipeBase &R : Header->phis()) {
822-
if (auto *FOR = dyn_cast<VPFirstOrderRecurrencePHIRecipe>(&R)) {
823-
auto *VecPhi = cast<PHINode>(State->get(FOR, 0));
824-
825-
VPValue *PreviousDef = FOR->getBackedgeValue();
826-
Value *Incoming = State->get(PreviousDef, State->UF - 1);
827-
VecPhi->addIncoming(Incoming, VectorLatchBB);
822+
auto *PhiR = dyn_cast<VPWidenPHIRecipe>(&R);
823+
if (!PhiR || !(isa<VPFirstOrderRecurrencePHIRecipe>(&R) ||
824+
isa<VPReductionPHIRecipe>(&R)))
825+
continue;
826+
// For first-order recurrences and in-order reduction phis, only a single
827+
// part is generated, which provides the last part from the previous
828+
// iteration. Otherwise all UF parts are generated.
829+
bool SinglePartNeeded = isa<VPFirstOrderRecurrencePHIRecipe>(&R) ||
830+
cast<VPReductionPHIRecipe>(&R)->isOrdered();
831+
unsigned LastPartForNewPhi = SinglePartNeeded ? 1 : State->UF;
832+
for (unsigned Part = 0; Part < LastPartForNewPhi; ++Part) {
833+
Value *VecPhi = State->get(PhiR, Part);
834+
Value *Val = State->get(PhiR->getBackedgeValue(),
835+
SinglePartNeeded ? State->UF - 1 : Part);
836+
cast<PHINode>(VecPhi)->addIncoming(Val, VectorLatchBB);
828837
}
829838
}
830839

@@ -1319,6 +1328,9 @@ void VPReductionPHIRecipe::execute(VPTransformState &State) {
13191328
PHINode::Create(VecTy, 2, "vec.phi", &*HeaderBB->getFirstInsertionPt());
13201329
State.set(this, EntryPart, Part);
13211330
}
1331+
1332+
// Reductions do not have to start at zero. They can start with
1333+
// any loop invariant values.
13221334
VPValue *StartVPV = getStartValue();
13231335
Value *StartV = StartVPV->getLiveInIRValue();
13241336

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