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[PowerPC] Improved codegen related to xscvdpsxws/xscvdpuxws
This patch removes the uneccessary mf/mtvsr generated in conjunction with xscvdpsxws/xscvdpuxws. Differential revision: https://reviews.llvm.org/D109902
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+114
-86
lines changed

3 files changed

+114
-86
lines changed

‎llvm/lib/Target/PowerPC/PPCInstrVSX.td

Lines changed: 84 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2809,6 +2809,10 @@ def : Pat<(v2i64 (build_vector DblToLong.A, DblToLong.A)),
28092809
def : Pat<(v2i64 (build_vector DblToULong.A, DblToULong.A)),
28102810
(v2i64 (XXPERMDI (SUBREG_TO_REG (i64 1), (XSCVDPUXDS $A), sub_64),
28112811
(SUBREG_TO_REG (i64 1), (XSCVDPUXDS $A), sub_64), 0))>;
2812+
def : Pat<(v4i32 (PPCSToV DblToInt.A)),
2813+
(v4i32 (SUBREG_TO_REG (i64 1), (XSCVDPSXWS f64:$A), sub_64))>;
2814+
def : Pat<(v4i32 (PPCSToV DblToUInt.A)),
2815+
(v4i32 (SUBREG_TO_REG (i64 1), (XSCVDPUXWS f64:$A), sub_64))>;
28122816
defm : ScalToVecWPermute<
28132817
v4i32, FltToIntLoad.A,
28142818
(XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWSs (XFLOADf32 ForceXForm:$A)), sub_64), 1),
@@ -4138,12 +4142,52 @@ def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))),
41384142
(f64 (XSCVUXDDP (XXEXTRACTUW $A, 12)))>;
41394143
def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 0)),
41404144
(v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 0))>;
4145+
def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 0)),
4146+
(v4i32 (XXINSERTW v4i32:$A,
4147+
(SUBREG_TO_REG (i64 1),
4148+
(XSCVDPSXWS f64:$B), sub_64),
4149+
0))>;
4150+
def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 0)),
4151+
(v4i32 (XXINSERTW v4i32:$A,
4152+
(SUBREG_TO_REG (i64 1),
4153+
(XSCVDPUXWS f64:$B), sub_64),
4154+
0))>;
41414155
def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 1)),
41424156
(v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 4))>;
4157+
def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 1)),
4158+
(v4i32 (XXINSERTW v4i32:$A,
4159+
(SUBREG_TO_REG (i64 1),
4160+
(XSCVDPSXWS f64:$B), sub_64),
4161+
4))>;
4162+
def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 1)),
4163+
(v4i32 (XXINSERTW v4i32:$A,
4164+
(SUBREG_TO_REG (i64 1),
4165+
(XSCVDPUXWS f64:$B), sub_64),
4166+
4))>;
41434167
def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 2)),
41444168
(v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 8))>;
4169+
def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 2)),
4170+
(v4i32 (XXINSERTW v4i32:$A,
4171+
(SUBREG_TO_REG (i64 1),
4172+
(XSCVDPSXWS f64:$B), sub_64),
4173+
8))>;
4174+
def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 2)),
4175+
(v4i32 (XXINSERTW v4i32:$A,
4176+
(SUBREG_TO_REG (i64 1),
4177+
(XSCVDPUXWS f64:$B), sub_64),
4178+
8))>;
41454179
def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 3)),
41464180
(v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 12))>;
4181+
def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 3)),
4182+
(v4i32 (XXINSERTW v4i32:$A,
4183+
(SUBREG_TO_REG (i64 1),
4184+
(XSCVDPSXWS f64:$B), sub_64),
4185+
12))>;
4186+
def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 3)),
4187+
(v4i32 (XXINSERTW v4i32:$A,
4188+
(SUBREG_TO_REG (i64 1),
4189+
(XSCVDPUXWS f64:$B), sub_64),
4190+
12))>;
41474191
def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 0)),
41484192
(v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 0))>;
41494193
def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 1)),
@@ -4382,12 +4426,52 @@ def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))),
43824426
(f64 (XSCVUXDDP (XXEXTRACTUW $A, 0)))>;
43834427
def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 0)),
43844428
(v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 12))>;
4429+
def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 0)),
4430+
(v4i32 (XXINSERTW v4i32:$A,
4431+
(SUBREG_TO_REG (i64 1),
4432+
(XSCVDPSXWS f64:$B), sub_64),
4433+
12))>;
4434+
def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 0)),
4435+
(v4i32 (XXINSERTW v4i32:$A,
4436+
(SUBREG_TO_REG (i64 1),
4437+
(XSCVDPUXWS f64:$B), sub_64),
4438+
12))>;
43854439
def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 1)),
43864440
(v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 8))>;
4441+
def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 1)),
4442+
(v4i32 (XXINSERTW v4i32:$A,
4443+
(SUBREG_TO_REG (i64 1),
4444+
(XSCVDPSXWS f64:$B), sub_64),
4445+
8))>;
4446+
def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 1)),
4447+
(v4i32 (XXINSERTW v4i32:$A,
4448+
(SUBREG_TO_REG (i64 1),
4449+
(XSCVDPUXWS f64:$B), sub_64),
4450+
8))>;
43874451
def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 2)),
43884452
(v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 4))>;
4453+
def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 2)),
4454+
(v4i32 (XXINSERTW v4i32:$A,
4455+
(SUBREG_TO_REG (i64 1),
4456+
(XSCVDPSXWS f64:$B), sub_64),
4457+
4))>;
4458+
def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 2)),
4459+
(v4i32 (XXINSERTW v4i32:$A,
4460+
(SUBREG_TO_REG (i64 1),
4461+
(XSCVDPUXWS f64:$B), sub_64),
4462+
4))>;
43894463
def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 3)),
43904464
(v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 0))>;
4465+
def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 3)),
4466+
(v4i32 (XXINSERTW v4i32:$A,
4467+
(SUBREG_TO_REG (i64 1),
4468+
(XSCVDPSXWS f64:$B), sub_64),
4469+
0))>;
4470+
def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 3)),
4471+
(v4i32 (XXINSERTW v4i32:$A,
4472+
(SUBREG_TO_REG (i64 1),
4473+
(XSCVDPUXWS f64:$B), sub_64),
4474+
0))>;
43914475
def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 0)),
43924476
(v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 12))>;
43934477
def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 1)),

‎llvm/test/CodeGen/PowerPC/test-vector-insert.ll

Lines changed: 18 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -17,8 +17,8 @@
1717
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
1818
; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
1919
; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-BE-P9
20-
; xscvdpsxws and uxws is only available on Power7 and above
21-
; Codgen is different for LE Power7 and Power8
20+
; xscvdpsxws and xscvdpsxws is only available on Power7 and above
21+
; Codgen is different for Power7, Power8, and Power9.
2222

2323
define dso_local <4 x i32> @test(<4 x i32> %a, double %b) {
2424
; CHECK-LE-P7-LABEL: test:
@@ -38,20 +38,16 @@ define dso_local <4 x i32> @test(<4 x i32> %a, double %b) {
3838
;
3939
; CHECK-LE-P8-LABEL: test:
4040
; CHECK-LE-P8: # %bb.0: # %entry
41-
; CHECK-LE-P8-NEXT: xscvdpsxws f0, f1
41+
; CHECK-LE-P8-NEXT: xscvdpsxws v3, f1
4242
; CHECK-LE-P8-NEXT: addis r3, r2, .LCPI0_0@toc@ha
4343
; CHECK-LE-P8-NEXT: addi r3, r3, .LCPI0_0@toc@l
44-
; CHECK-LE-P8-NEXT: lvx v3, 0, r3
45-
; CHECK-LE-P8-NEXT: mffprwz r4, f0
46-
; CHECK-LE-P8-NEXT: mtvsrwz v4, r4
47-
; CHECK-LE-P8-NEXT: vperm v2, v4, v2, v3
44+
; CHECK-LE-P8-NEXT: lvx v4, 0, r3
45+
; CHECK-LE-P8-NEXT: vperm v2, v3, v2, v4
4846
; CHECK-LE-P8-NEXT: blr
4947
;
5048
; CHECK-LE-P9-LABEL: test:
5149
; CHECK-LE-P9: # %bb.0: # %entry
5250
; CHECK-LE-P9-NEXT: xscvdpsxws f0, f1
53-
; CHECK-LE-P9-NEXT: mffprwz r3, f0
54-
; CHECK-LE-P9-NEXT: mtfprwz f0, r3
5551
; CHECK-LE-P9-NEXT: xxinsertw v2, vs0, 0
5652
; CHECK-LE-P9-NEXT: blr
5753
;
@@ -70,9 +66,7 @@ define dso_local <4 x i32> @test(<4 x i32> %a, double %b) {
7066
;
7167
; CHECK-BE-P8-LABEL: test:
7268
; CHECK-BE-P8: # %bb.0: # %entry
73-
; CHECK-BE-P8-NEXT: xscvdpsxws f0, f1
74-
; CHECK-BE-P8-NEXT: mffprwz r3, f0
75-
; CHECK-BE-P8-NEXT: mtvsrwz v3, r3
69+
; CHECK-BE-P8-NEXT: xscvdpsxws v3, f1
7670
; CHECK-BE-P8-NEXT: vmrghw v3, v2, v3
7771
; CHECK-BE-P8-NEXT: xxsldwi vs0, v3, v2, 3
7872
; CHECK-BE-P8-NEXT: xxsldwi v2, vs0, vs0, 1
@@ -81,8 +75,6 @@ define dso_local <4 x i32> @test(<4 x i32> %a, double %b) {
8175
; CHECK-BE-P9-LABEL: test:
8276
; CHECK-BE-P9: # %bb.0: # %entry
8377
; CHECK-BE-P9-NEXT: xscvdpsxws f0, f1
84-
; CHECK-BE-P9-NEXT: mffprwz r3, f0
85-
; CHECK-BE-P9-NEXT: mtfprwz f0, r3
8678
; CHECK-BE-P9-NEXT: xxinsertw v2, vs0, 12
8779
; CHECK-BE-P9-NEXT: blr
8880
entry:
@@ -109,20 +101,16 @@ define dso_local <4 x i32> @test2(<4 x i32> %a, float %b) {
109101
;
110102
; CHECK-LE-P8-LABEL: test2:
111103
; CHECK-LE-P8: # %bb.0: # %entry
112-
; CHECK-LE-P8-NEXT: xscvdpsxws f0, f1
104+
; CHECK-LE-P8-NEXT: xscvdpsxws v3, f1
113105
; CHECK-LE-P8-NEXT: addis r3, r2, .LCPI1_0@toc@ha
114106
; CHECK-LE-P8-NEXT: addi r3, r3, .LCPI1_0@toc@l
115-
; CHECK-LE-P8-NEXT: lvx v3, 0, r3
116-
; CHECK-LE-P8-NEXT: mffprwz r4, f0
117-
; CHECK-LE-P8-NEXT: mtvsrwz v4, r4
118-
; CHECK-LE-P8-NEXT: vperm v2, v4, v2, v3
107+
; CHECK-LE-P8-NEXT: lvx v4, 0, r3
108+
; CHECK-LE-P8-NEXT: vperm v2, v3, v2, v4
119109
; CHECK-LE-P8-NEXT: blr
120110
;
121111
; CHECK-LE-P9-LABEL: test2:
122112
; CHECK-LE-P9: # %bb.0: # %entry
123113
; CHECK-LE-P9-NEXT: xscvdpsxws f0, f1
124-
; CHECK-LE-P9-NEXT: mffprwz r3, f0
125-
; CHECK-LE-P9-NEXT: mtfprwz f0, r3
126114
; CHECK-LE-P9-NEXT: xxinsertw v2, vs0, 0
127115
; CHECK-LE-P9-NEXT: blr
128116
;
@@ -141,9 +129,7 @@ define dso_local <4 x i32> @test2(<4 x i32> %a, float %b) {
141129
;
142130
; CHECK-BE-P8-LABEL: test2:
143131
; CHECK-BE-P8: # %bb.0: # %entry
144-
; CHECK-BE-P8-NEXT: xscvdpsxws f0, f1
145-
; CHECK-BE-P8-NEXT: mffprwz r3, f0
146-
; CHECK-BE-P8-NEXT: mtvsrwz v3, r3
132+
; CHECK-BE-P8-NEXT: xscvdpsxws v3, f1
147133
; CHECK-BE-P8-NEXT: vmrghw v3, v2, v3
148134
; CHECK-BE-P8-NEXT: xxsldwi vs0, v3, v2, 3
149135
; CHECK-BE-P8-NEXT: xxsldwi v2, vs0, vs0, 1
@@ -152,8 +138,6 @@ define dso_local <4 x i32> @test2(<4 x i32> %a, float %b) {
152138
; CHECK-BE-P9-LABEL: test2:
153139
; CHECK-BE-P9: # %bb.0: # %entry
154140
; CHECK-BE-P9-NEXT: xscvdpsxws f0, f1
155-
; CHECK-BE-P9-NEXT: mffprwz r3, f0
156-
; CHECK-BE-P9-NEXT: mtfprwz f0, r3
157141
; CHECK-BE-P9-NEXT: xxinsertw v2, vs0, 12
158142
; CHECK-BE-P9-NEXT: blr
159143
entry:
@@ -180,20 +164,16 @@ define dso_local <4 x i32> @test3(<4 x i32> %a, double %b) {
180164
;
181165
; CHECK-LE-P8-LABEL: test3:
182166
; CHECK-LE-P8: # %bb.0: # %entry
183-
; CHECK-LE-P8-NEXT: xscvdpuxws f0, f1
167+
; CHECK-LE-P8-NEXT: xscvdpuxws v3, f1
184168
; CHECK-LE-P8-NEXT: addis r3, r2, .LCPI2_0@toc@ha
185169
; CHECK-LE-P8-NEXT: addi r3, r3, .LCPI2_0@toc@l
186-
; CHECK-LE-P8-NEXT: lvx v3, 0, r3
187-
; CHECK-LE-P8-NEXT: mffprwz r4, f0
188-
; CHECK-LE-P8-NEXT: mtvsrwz v4, r4
189-
; CHECK-LE-P8-NEXT: vperm v2, v4, v2, v3
170+
; CHECK-LE-P8-NEXT: lvx v4, 0, r3
171+
; CHECK-LE-P8-NEXT: vperm v2, v3, v2, v4
190172
; CHECK-LE-P8-NEXT: blr
191173
;
192174
; CHECK-LE-P9-LABEL: test3:
193175
; CHECK-LE-P9: # %bb.0: # %entry
194176
; CHECK-LE-P9-NEXT: xscvdpuxws f0, f1
195-
; CHECK-LE-P9-NEXT: mffprwz r3, f0
196-
; CHECK-LE-P9-NEXT: mtfprwz f0, r3
197177
; CHECK-LE-P9-NEXT: xxinsertw v2, vs0, 0
198178
; CHECK-LE-P9-NEXT: blr
199179
;
@@ -212,9 +192,7 @@ define dso_local <4 x i32> @test3(<4 x i32> %a, double %b) {
212192
;
213193
; CHECK-BE-P8-LABEL: test3:
214194
; CHECK-BE-P8: # %bb.0: # %entry
215-
; CHECK-BE-P8-NEXT: xscvdpuxws f0, f1
216-
; CHECK-BE-P8-NEXT: mffprwz r3, f0
217-
; CHECK-BE-P8-NEXT: mtvsrwz v3, r3
195+
; CHECK-BE-P8-NEXT: xscvdpuxws v3, f1
218196
; CHECK-BE-P8-NEXT: vmrghw v3, v2, v3
219197
; CHECK-BE-P8-NEXT: xxsldwi vs0, v3, v2, 3
220198
; CHECK-BE-P8-NEXT: xxsldwi v2, vs0, vs0, 1
@@ -223,8 +201,6 @@ define dso_local <4 x i32> @test3(<4 x i32> %a, double %b) {
223201
; CHECK-BE-P9-LABEL: test3:
224202
; CHECK-BE-P9: # %bb.0: # %entry
225203
; CHECK-BE-P9-NEXT: xscvdpuxws f0, f1
226-
; CHECK-BE-P9-NEXT: mffprwz r3, f0
227-
; CHECK-BE-P9-NEXT: mtfprwz f0, r3
228204
; CHECK-BE-P9-NEXT: xxinsertw v2, vs0, 12
229205
; CHECK-BE-P9-NEXT: blr
230206
entry:
@@ -251,20 +227,16 @@ define dso_local <4 x i32> @test4(<4 x i32> %a, float %b) {
251227
;
252228
; CHECK-LE-P8-LABEL: test4:
253229
; CHECK-LE-P8: # %bb.0: # %entry
254-
; CHECK-LE-P8-NEXT: xscvdpuxws f0, f1
230+
; CHECK-LE-P8-NEXT: xscvdpuxws v3, f1
255231
; CHECK-LE-P8-NEXT: addis r3, r2, .LCPI3_0@toc@ha
256232
; CHECK-LE-P8-NEXT: addi r3, r3, .LCPI3_0@toc@l
257-
; CHECK-LE-P8-NEXT: lvx v3, 0, r3
258-
; CHECK-LE-P8-NEXT: mffprwz r4, f0
259-
; CHECK-LE-P8-NEXT: mtvsrwz v4, r4
260-
; CHECK-LE-P8-NEXT: vperm v2, v4, v2, v3
233+
; CHECK-LE-P8-NEXT: lvx v4, 0, r3
234+
; CHECK-LE-P8-NEXT: vperm v2, v3, v2, v4
261235
; CHECK-LE-P8-NEXT: blr
262236
;
263237
; CHECK-LE-P9-LABEL: test4:
264238
; CHECK-LE-P9: # %bb.0: # %entry
265239
; CHECK-LE-P9-NEXT: xscvdpuxws f0, f1
266-
; CHECK-LE-P9-NEXT: mffprwz r3, f0
267-
; CHECK-LE-P9-NEXT: mtfprwz f0, r3
268240
; CHECK-LE-P9-NEXT: xxinsertw v2, vs0, 0
269241
; CHECK-LE-P9-NEXT: blr
270242
;
@@ -283,9 +255,7 @@ define dso_local <4 x i32> @test4(<4 x i32> %a, float %b) {
283255
;
284256
; CHECK-BE-P8-LABEL: test4:
285257
; CHECK-BE-P8: # %bb.0: # %entry
286-
; CHECK-BE-P8-NEXT: xscvdpuxws f0, f1
287-
; CHECK-BE-P8-NEXT: mffprwz r3, f0
288-
; CHECK-BE-P8-NEXT: mtvsrwz v3, r3
258+
; CHECK-BE-P8-NEXT: xscvdpuxws v3, f1
289259
; CHECK-BE-P8-NEXT: vmrghw v3, v2, v3
290260
; CHECK-BE-P8-NEXT: xxsldwi vs0, v3, v2, 3
291261
; CHECK-BE-P8-NEXT: xxsldwi v2, vs0, vs0, 1
@@ -294,8 +264,6 @@ define dso_local <4 x i32> @test4(<4 x i32> %a, float %b) {
294264
; CHECK-BE-P9-LABEL: test4:
295265
; CHECK-BE-P9: # %bb.0: # %entry
296266
; CHECK-BE-P9-NEXT: xscvdpuxws f0, f1
297-
; CHECK-BE-P9-NEXT: mffprwz r3, f0
298-
; CHECK-BE-P9-NEXT: mtfprwz f0, r3
299267
; CHECK-BE-P9-NEXT: xxinsertw v2, vs0, 12
300268
; CHECK-BE-P9-NEXT: blr
301269
entry:

‎llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll

Lines changed: 12 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -13,39 +13,27 @@ define i64 @test2elt(<2 x double> %a) local_unnamed_addr #0 {
1313
; CHECK-P8-LABEL: test2elt:
1414
; CHECK-P8: # %bb.0: # %entry
1515
; CHECK-P8-NEXT: xxswapd vs0, v2
16-
; CHECK-P8-NEXT: xscvdpuxws f1, v2
17-
; CHECK-P8-NEXT: xscvdpuxws f0, f0
18-
; CHECK-P8-NEXT: mffprwz r3, f1
19-
; CHECK-P8-NEXT: mtvsrwz v2, r3
20-
; CHECK-P8-NEXT: mffprwz r4, f0
21-
; CHECK-P8-NEXT: mtvsrwz v3, r4
16+
; CHECK-P8-NEXT: xscvdpuxws v2, v2
17+
; CHECK-P8-NEXT: xscvdpuxws v3, f0
2218
; CHECK-P8-NEXT: vmrghw v2, v2, v3
2319
; CHECK-P8-NEXT: xxswapd vs0, v2
2420
; CHECK-P8-NEXT: mffprd r3, f0
2521
; CHECK-P8-NEXT: blr
2622
;
2723
; CHECK-P9-LABEL: test2elt:
2824
; CHECK-P9: # %bb.0: # %entry
29-
; CHECK-P9-NEXT: xscvdpuxws f0, v2
30-
; CHECK-P9-NEXT: mffprwz r3, f0
3125
; CHECK-P9-NEXT: xxswapd vs0, v2
32-
; CHECK-P9-NEXT: mtvsrwz v3, r3
33-
; CHECK-P9-NEXT: xscvdpuxws f0, f0
34-
; CHECK-P9-NEXT: mffprwz r3, f0
35-
; CHECK-P9-NEXT: mtvsrwz v2, r3
26+
; CHECK-P9-NEXT: xscvdpuxws v3, v2
27+
; CHECK-P9-NEXT: xscvdpuxws v2, f0
3628
; CHECK-P9-NEXT: vmrghw v2, v3, v2
3729
; CHECK-P9-NEXT: mfvsrld r3, v2
3830
; CHECK-P9-NEXT: blr
3931
;
4032
; CHECK-BE-LABEL: test2elt:
4133
; CHECK-BE: # %bb.0: # %entry
42-
; CHECK-BE-NEXT: xscvdpuxws f0, v2
43-
; CHECK-BE-NEXT: mffprwz r3, f0
4434
; CHECK-BE-NEXT: xxswapd vs0, v2
45-
; CHECK-BE-NEXT: mtvsrwz v3, r3
46-
; CHECK-BE-NEXT: xscvdpuxws f0, f0
47-
; CHECK-BE-NEXT: mffprwz r3, f0
48-
; CHECK-BE-NEXT: mtvsrwz v2, r3
35+
; CHECK-BE-NEXT: xscvdpuxws v3, v2
36+
; CHECK-BE-NEXT: xscvdpuxws v2, f0
4937
; CHECK-BE-NEXT: vmrgow v2, v3, v2
5038
; CHECK-BE-NEXT: mfvsrd r3, v2
5139
; CHECK-BE-NEXT: blr
@@ -305,39 +293,27 @@ define i64 @test2elt_signed(<2 x double> %a) local_unnamed_addr #0 {
305293
; CHECK-P8-LABEL: test2elt_signed:
306294
; CHECK-P8: # %bb.0: # %entry
307295
; CHECK-P8-NEXT: xxswapd vs0, v2
308-
; CHECK-P8-NEXT: xscvdpsxws f1, v2
309-
; CHECK-P8-NEXT: xscvdpsxws f0, f0
310-
; CHECK-P8-NEXT: mffprwz r3, f1
311-
; CHECK-P8-NEXT: mtvsrwz v2, r3
312-
; CHECK-P8-NEXT: mffprwz r4, f0
313-
; CHECK-P8-NEXT: mtvsrwz v3, r4
296+
; CHECK-P8-NEXT: xscvdpsxws v2, v2
297+
; CHECK-P8-NEXT: xscvdpsxws v3, f0
314298
; CHECK-P8-NEXT: vmrghw v2, v2, v3
315299
; CHECK-P8-NEXT: xxswapd vs0, v2
316300
; CHECK-P8-NEXT: mffprd r3, f0
317301
; CHECK-P8-NEXT: blr
318302
;
319303
; CHECK-P9-LABEL: test2elt_signed:
320304
; CHECK-P9: # %bb.0: # %entry
321-
; CHECK-P9-NEXT: xscvdpsxws f0, v2
322-
; CHECK-P9-NEXT: mffprwz r3, f0
323305
; CHECK-P9-NEXT: xxswapd vs0, v2
324-
; CHECK-P9-NEXT: mtvsrwz v3, r3
325-
; CHECK-P9-NEXT: xscvdpsxws f0, f0
326-
; CHECK-P9-NEXT: mffprwz r3, f0
327-
; CHECK-P9-NEXT: mtvsrwz v2, r3
306+
; CHECK-P9-NEXT: xscvdpsxws v3, v2
307+
; CHECK-P9-NEXT: xscvdpsxws v2, f0
328308
; CHECK-P9-NEXT: vmrghw v2, v3, v2
329309
; CHECK-P9-NEXT: mfvsrld r3, v2
330310
; CHECK-P9-NEXT: blr
331311
;
332312
; CHECK-BE-LABEL: test2elt_signed:
333313
; CHECK-BE: # %bb.0: # %entry
334-
; CHECK-BE-NEXT: xscvdpsxws f0, v2
335-
; CHECK-BE-NEXT: mffprwz r3, f0
336314
; CHECK-BE-NEXT: xxswapd vs0, v2
337-
; CHECK-BE-NEXT: mtvsrwz v3, r3
338-
; CHECK-BE-NEXT: xscvdpsxws f0, f0
339-
; CHECK-BE-NEXT: mffprwz r3, f0
340-
; CHECK-BE-NEXT: mtvsrwz v2, r3
315+
; CHECK-BE-NEXT: xscvdpsxws v3, v2
316+
; CHECK-BE-NEXT: xscvdpsxws v2, f0
341317
; CHECK-BE-NEXT: vmrgow v2, v3, v2
342318
; CHECK-BE-NEXT: mfvsrd r3, v2
343319
; CHECK-BE-NEXT: blr

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