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8 | 8 | //
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9 | 9 | // This file defines the basic operations for the AMX dialect.
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10 | 10 | //
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11 |
| -// The Intel Advanced Matrix Extensions (AMX) provides a tile matrix |
| 11 | +// The Intel Advanced Matrix Extensions (AMX) provide a tile matrix |
12 | 12 | // multiply unit (TMUL), a tile control register (TILECFG), and eight
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13 | 13 | // tile registers TMM0 through TMM7 (TILEDATA).
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14 | 14 | //
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@@ -38,6 +38,23 @@ include "mlir/Interfaces/SideEffectInterfaces.td"
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38 | 38 | def AMX_Dialect : Dialect {
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39 | 39 | let name = "amx";
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40 | 40 | let cppNamespace = "::mlir::amx";
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| 41 | + let description = [{ |
| 42 | + The Intel Advanced Matrix Extensions (AMX) provide a tile matrix |
| 43 | + multiply unit (TMUL), a tile control register (TILECFG), and eight |
| 44 | + tile registers TMM0 through TMM7 (TILEDATA). |
| 45 | + |
| 46 | + This `AMX` dialect provides a bridge between MLIR concepts such as |
| 47 | + vectors and memrefs and the lower level LLVM IR support of AMX. |
| 48 | + The dialect is split into user-facing AMX ops (AMX_Op) and |
| 49 | + backend-facing intrinsic ops (AMX_IntrOp). |
| 50 | + |
| 51 | + Note that since configuration changes (implicit at dialect level) are |
| 52 | + costly, it is highly recommended to use the AMX dialect on same-shaped |
| 53 | + vectors, at least within a single method. |
| 54 | + |
| 55 | + For details, see the Intel documentation: |
| 56 | + https://software.intel.com/content/www/us/en/develop/articles/intel-sdm.html |
| 57 | + }]; |
41 | 58 | }
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42 | 59 |
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43 | 60 | //===----------------------------------------------------------------------===//
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@@ -203,7 +220,7 @@ def TileMulIOp : AMX_Op<"tile_muli", [NoSideEffect, AllTypesMatch<["acc", "res"]
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203 | 220 | Example:
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204 | 221 |
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205 | 222 | ```mlir
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206 |
| - %0 = amx.tile_muli %a zext, %b zext, %c |
| 223 | + %0 = amx.tile_muli %a zext, %b zext, %c |
207 | 224 | : vector<16x64xi8>, vector<16x64xi8>, vector<16x16xi32>
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208 | 225 | ```
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209 | 226 | }];
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