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[AArch64][SVE] Add break intrinsics
Summary: Implements the following intrinsics: * @llvm.aarch64.sve.brka * @llvm.aarch64.sve.brka.z * @llvm.aarch64.sve.brkb * @llvm.aarch64.sve.brkb.z * @llvm.aarch64.sve.brkn.z * @llvm.aarch64.sve.brkpa.z * @llvm.aarch64.sve.brkpb.z Reviewers: sdesmalen, efriedma, dancgr, mgudim, cameron.mcinally, rengolin Reviewed By: sdesmalen Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72393
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4 files changed

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‎llvm/include/llvm/IR/IntrinsicsAArch64.td

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1548,6 +1548,13 @@ def int_aarch64_sve_ptrue : AdvSIMD_SVE_PTRUE_Intrinsic;
15481548

15491549
def int_aarch64_sve_and_z : AdvSIMD_Pred2VectorArg_Intrinsic;
15501550
def int_aarch64_sve_bic_z : AdvSIMD_Pred2VectorArg_Intrinsic;
1551+
def int_aarch64_sve_brka : AdvSIMD_Merged1VectorArg_Intrinsic;
1552+
def int_aarch64_sve_brka_z : AdvSIMD_Pred1VectorArg_Intrinsic;
1553+
def int_aarch64_sve_brkb : AdvSIMD_Merged1VectorArg_Intrinsic;
1554+
def int_aarch64_sve_brkb_z : AdvSIMD_Pred1VectorArg_Intrinsic;
1555+
def int_aarch64_sve_brkn_z : AdvSIMD_Pred2VectorArg_Intrinsic;
1556+
def int_aarch64_sve_brkpa_z : AdvSIMD_Pred2VectorArg_Intrinsic;
1557+
def int_aarch64_sve_brkpb_z : AdvSIMD_Pred2VectorArg_Intrinsic;
15511558
def int_aarch64_sve_eor_z : AdvSIMD_Pred2VectorArg_Intrinsic;
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def int_aarch64_sve_nand_z : AdvSIMD_Pred2VectorArg_Intrinsic;
15531560
def int_aarch64_sve_nor_z : AdvSIMD_Pred2VectorArg_Intrinsic;

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -290,20 +290,20 @@ let Predicates = [HasSVE] in {
290290
def MOVPRFX_ZZ : sve_int_bin_cons_misc_0_c<0b00000001, "movprfx", ZPRAny>;
291291
defm FEXPA_ZZ : sve_int_bin_cons_misc_0_c_fexpa<"fexpa", int_aarch64_sve_fexpa_x>;
292292

293-
def BRKPA_PPzPP : sve_int_brkp<0b00, "brkpa">;
294-
def BRKPAS_PPzPP : sve_int_brkp<0b10, "brkpas">;
295-
def BRKPB_PPzPP : sve_int_brkp<0b01, "brkpb">;
296-
def BRKPBS_PPzPP : sve_int_brkp<0b11, "brkpbs">;
297-
298-
def BRKN_PPzP : sve_int_brkn<0b0, "brkn">;
299-
def BRKNS_PPzP : sve_int_brkn<0b1, "brkns">;
300-
301-
defm BRKA_PPzP : sve_int_break_z<0b000, "brka">;
302-
defm BRKA_PPmP : sve_int_break_m<0b001, "brka">;
303-
defm BRKAS_PPzP : sve_int_break_z<0b010, "brkas">;
304-
defm BRKB_PPzP : sve_int_break_z<0b100, "brkb">;
305-
defm BRKB_PPmP : sve_int_break_m<0b101, "brkb">;
306-
defm BRKBS_PPzP : sve_int_break_z<0b110, "brkbs">;
293+
defm BRKPA_PPzPP : sve_int_brkp<0b00, "brkpa", int_aarch64_sve_brkpa_z>;
294+
defm BRKPAS_PPzPP : sve_int_brkp<0b10, "brkpas", null_frag>;
295+
defm BRKPB_PPzPP : sve_int_brkp<0b01, "brkpb", int_aarch64_sve_brkpb_z>;
296+
defm BRKPBS_PPzPP : sve_int_brkp<0b11, "brkpbs", null_frag>;
297+
298+
defm BRKN_PPzP : sve_int_brkn<0b0, "brkn", int_aarch64_sve_brkn_z>;
299+
defm BRKNS_PPzP : sve_int_brkn<0b1, "brkns", null_frag>;
300+
301+
defm BRKA_PPzP : sve_int_break_z<0b000, "brka", int_aarch64_sve_brka_z>;
302+
defm BRKA_PPmP : sve_int_break_m<0b001, "brka", int_aarch64_sve_brka>;
303+
defm BRKAS_PPzP : sve_int_break_z<0b010, "brkas", null_frag>;
304+
defm BRKB_PPzP : sve_int_break_z<0b100, "brkb", int_aarch64_sve_brkb_z>;
305+
defm BRKB_PPmP : sve_int_break_m<0b101, "brkb", int_aarch64_sve_brkb>;
306+
defm BRKBS_PPzP : sve_int_break_z<0b110, "brkbs", null_frag>;
307307

308308
def PTEST_PP : sve_int_ptest<0b010000, "ptest">;
309309
def PFALSE : sve_int_pfalse<0b000000, "pfalse">;

‎llvm/lib/Target/AArch64/SVEInstrFormats.td

Lines changed: 18 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6600,6 +6600,12 @@ class sve_int_brkp<bits<2> opc, string asm>
66006600
let Defs = !if(!eq (opc{1}, 1), [NZCV], []);
66016601
}
66026602

6603+
multiclass sve_int_brkp<bits<2> opc, string asm, SDPatternOperator op> {
6604+
def NAME : sve_int_brkp<opc, asm>;
6605+
6606+
def : SVE_3_Op_Pat<nxv16i1, op, nxv16i1, nxv16i1, nxv16i1, !cast<Instruction>(NAME)>;
6607+
}
6608+
66036609

66046610
//===----------------------------------------------------------------------===//
66056611
// SVE Partition Break Group
@@ -6626,6 +6632,12 @@ class sve_int_brkn<bit S, string asm>
66266632
let Defs = !if(!eq (S, 0b1), [NZCV], []);
66276633
}
66286634

6635+
multiclass sve_int_brkn<bits<1> opc, string asm, SDPatternOperator op> {
6636+
def NAME : sve_int_brkn<opc, asm>;
6637+
6638+
def : SVE_3_Op_Pat<nxv16i1, op, nxv16i1, nxv16i1, nxv16i1, !cast<Instruction>(NAME)>;
6639+
}
6640+
66296641
class sve_int_break<bits<3> opc, string asm, string suffix, dag iops>
66306642
: I<(outs PPR8:$Pd), iops,
66316643
asm, "\t$Pd, $Pg"#suffix#", $Pn",
@@ -6648,12 +6660,16 @@ class sve_int_break<bits<3> opc, string asm, string suffix, dag iops>
66486660

66496661
}
66506662

6651-
multiclass sve_int_break_m<bits<3> opc, string asm> {
6663+
multiclass sve_int_break_m<bits<3> opc, string asm, SDPatternOperator op> {
66526664
def NAME : sve_int_break<opc, asm, "/m", (ins PPR8:$_Pd, PPRAny:$Pg, PPR8:$Pn)>;
6665+
6666+
def : SVE_3_Op_Pat<nxv16i1, op, nxv16i1, nxv16i1, nxv16i1, !cast<Instruction>(NAME)>;
66536667
}
66546668

6655-
multiclass sve_int_break_z<bits<3> opc, string asm> {
6669+
multiclass sve_int_break_z<bits<3> opc, string asm, SDPatternOperator op> {
66566670
def NAME : sve_int_break<opc, asm, "/z", (ins PPRAny:$Pg, PPR8:$Pn)>;
6671+
6672+
def : SVE_2_Op_Pat<nxv16i1, op, nxv16i1, nxv16i1, !cast<Instruction>(NAME)>;
66576673
}
66586674

66596675
//===----------------------------------------------------------------------===//

‎llvm/test/CodeGen/AArch64/sve-intrinsics-pred-operations.ll

Lines changed: 97 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,94 @@
11
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
22

3+
;
4+
; BRKA
5+
;
6+
7+
define <vscale x 16 x i1> @brka_m_b8(<vscale x 16 x i1> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
8+
; CHECK-LABEL: brka_m_b8:
9+
; CHECK: brka p0.b, p1/m, p2.b
10+
; CHECK-NEXT: ret
11+
%out = call <vscale x 16 x i1> @llvm.aarch64.sve.brka.nxv16i1(<vscale x 16 x i1> %inactive,
12+
<vscale x 16 x i1> %pg,
13+
<vscale x 16 x i1> %a)
14+
ret <vscale x 16 x i1> %out
15+
}
16+
17+
define <vscale x 16 x i1> @brka_z_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
18+
; CHECK-LABEL: brka_z_b8:
19+
; CHECK: brka p0.b, p0/z, p1.b
20+
; CHECK-NEXT: ret
21+
%out = call <vscale x 16 x i1> @llvm.aarch64.sve.brka.z.nxv16i1(<vscale x 16 x i1> %pg,
22+
<vscale x 16 x i1> %a)
23+
ret <vscale x 16 x i1> %out
24+
}
25+
26+
;
27+
; BRKB
28+
;
29+
30+
define <vscale x 16 x i1> @brkb_m_b8(<vscale x 16 x i1> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
31+
; CHECK-LABEL: brkb_m_b8:
32+
; CHECK: brkb p0.b, p1/m, p2.b
33+
; CHECK-NEXT: ret
34+
%out = call <vscale x 16 x i1> @llvm.aarch64.sve.brkb.nxv16i1(<vscale x 16 x i1> %inactive,
35+
<vscale x 16 x i1> %pg,
36+
<vscale x 16 x i1> %a)
37+
ret <vscale x 16 x i1> %out
38+
}
39+
40+
define <vscale x 16 x i1> @brkb_z_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
41+
; CHECK-LABEL: brkb_z_b8:
42+
; CHECK: brkb p0.b, p0/z, p1.b
43+
; CHECK-NEXT: ret
44+
%out = call <vscale x 16 x i1> @llvm.aarch64.sve.brkb.z.nxv16i1(<vscale x 16 x i1> %pg,
45+
<vscale x 16 x i1> %a)
46+
ret <vscale x 16 x i1> %out
47+
}
48+
49+
;
50+
; BRKN
51+
;
52+
53+
define <vscale x 16 x i1> @brkn_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
54+
; CHECK-LABEL: brkn_b8:
55+
; CHECK: brkn p2.b, p0/z, p1.b, p2.b
56+
; CHECK-NEXT: mov p0.b, p2.b
57+
; CHECK-NEXT: ret
58+
%out = call <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1> %pg,
59+
<vscale x 16 x i1> %a,
60+
<vscale x 16 x i1> %b)
61+
ret <vscale x 16 x i1> %out
62+
}
63+
64+
;
65+
; BRKPA
66+
;
67+
68+
define <vscale x 16 x i1> @brkpa_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
69+
; CHECK-LABEL: brkpa_b8:
70+
; CHECK: brkpa p0.b, p0/z, p1.b, p2.b
71+
; CHECK-NEXT: ret
72+
%out = call <vscale x 16 x i1> @llvm.aarch64.sve.brkpa.z.nxv16i1(<vscale x 16 x i1> %pg,
73+
<vscale x 16 x i1> %a,
74+
<vscale x 16 x i1> %b)
75+
ret <vscale x 16 x i1> %out
76+
}
77+
78+
;
79+
; BRKPB
80+
;
81+
82+
define <vscale x 16 x i1> @brkpb_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
83+
; CHECK-LABEL: brkpb_b8:
84+
; CHECK: brkpb p0.b, p0/z, p1.b, p2.b
85+
; CHECK-NEXT: ret
86+
%out = call <vscale x 16 x i1> @llvm.aarch64.sve.brkpb.z.nxv16i1(<vscale x 16 x i1> %pg,
87+
<vscale x 16 x i1> %a,
88+
<vscale x 16 x i1> %b)
89+
ret <vscale x 16 x i1> %out
90+
}
91+
392
;
493
; PFIRST
594
;
@@ -114,6 +203,14 @@ define <vscale x 2 x i1> @punpklo_b4(<vscale x 4 x i1> %a) {
114203
ret <vscale x 2 x i1> %res
115204
}
116205

206+
declare <vscale x 16 x i1> @llvm.aarch64.sve.brka.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
207+
declare <vscale x 16 x i1> @llvm.aarch64.sve.brka.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
208+
declare <vscale x 16 x i1> @llvm.aarch64.sve.brkb.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
209+
declare <vscale x 16 x i1> @llvm.aarch64.sve.brkb.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
210+
declare <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
211+
declare <vscale x 16 x i1> @llvm.aarch64.sve.brkpa.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
212+
declare <vscale x 16 x i1> @llvm.aarch64.sve.brkpb.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
213+
117214
declare <vscale x 16 x i1> @llvm.aarch64.sve.pfirst.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
118215

119216
declare <vscale x 16 x i1> @llvm.aarch64.sve.pnext.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)

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