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[RISCV][NFC] Remove LMUL from vmv.s.x and vmv.x.s scheduler classes
These instructions don't read or write register groups. We only pretend they do in intrinsics and pseudoinstructions. Differential Revision: https://reviews.llvm.org/D150238
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4 files changed

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‎llvm/lib/Target/RISCV/RISCVInstrInfoV.td

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1615,12 +1615,11 @@ def VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VR:$vd),
16151615
let vm = 1, RVVConstraint = NoConstraint in {
16161616
def VMV_X_S : RVInstV<0b010000, 0b00000, OPMVV, (outs GPR:$vd),
16171617
(ins VR:$vs2), "vmv.x.s", "$vd, $vs2">,
1618-
Sched<[WriteVIMovVX_WorstCase, ReadVIMovVX_WorstCase]>;
1618+
Sched<[WriteVIMovVX, ReadVIMovVX]>;
16191619
let Constraints = "$vd = $vd_wb" in
16201620
def VMV_S_X : RVInstV2<0b010000, 0b00000, OPMVX, (outs VR:$vd_wb),
16211621
(ins VR:$vd, GPR:$rs1), "vmv.s.x", "$vd, $rs1">,
1622-
Sched<[WriteVIMovXV_WorstCase, ReadVIMovXV_WorstCase,
1623-
ReadVIMovXX_WorstCase]>;
1622+
Sched<[WriteVIMovXV, ReadVIMovXV, ReadVIMovXX]>;
16241623
}
16251624

16261625
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
@@ -1634,12 +1633,11 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1,
16341633
// Floating-Point Scalar Move Instructions
16351634
def VFMV_F_S : RVInstV<0b010000, 0b00000, OPFVV, (outs FPR32:$vd),
16361635
(ins VR:$vs2), "vfmv.f.s", "$vd, $vs2">,
1637-
Sched<[WriteVFMovVF_WorstCase, ReadVFMovVF_WorstCase]>;
1636+
Sched<[WriteVFMovVF, ReadVFMovVF]>;
16381637
let Constraints = "$vd = $vd_wb" in
16391638
def VFMV_S_F : RVInstV2<0b010000, 0b00000, OPFVF, (outs VR:$vd_wb),
16401639
(ins VR:$vd, FPR32:$rs1), "vfmv.s.f", "$vd, $rs1">,
1641-
Sched<[WriteVFMovFV_WorstCase, ReadVFMovFV_WorstCase,
1642-
ReadVFMovFX_WorstCase]>;
1640+
Sched<[WriteVFMovFV, ReadVFMovFV, ReadVFMovFX]>;
16431641

16441642
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1
16451643

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 4 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -6178,24 +6178,19 @@ let Predicates = [HasVInstructions] in {
61786178
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
61796179
foreach m = MxList in {
61806180
defvar mx = m.MX;
6181-
defvar WriteVIMovVX_MX = !cast<SchedWrite>("WriteVIMovVX_" # mx);
6182-
defvar WriteVIMovXV_MX = !cast<SchedWrite>("WriteVIMovXV_" # mx);
6183-
defvar ReadVIMovVX_MX = !cast<SchedRead>("ReadVIMovVX_" # mx);
6184-
defvar ReadVIMovXV_MX = !cast<SchedRead>("ReadVIMovXV_" # mx);
6185-
defvar ReadVIMovXX_MX = !cast<SchedRead>("ReadVIMovXX_" # mx);
61866181
let VLMul = m.value in {
61876182
let HasSEWOp = 1, BaseInstr = VMV_X_S in
61886183
def PseudoVMV_X_S # "_" # mx:
61896184
Pseudo<(outs GPR:$rd), (ins m.vrclass:$rs2, ixlenimm:$sew), []>,
6190-
Sched<[WriteVIMovVX_MX, ReadVIMovVX_MX]>,
6185+
Sched<[WriteVIMovVX, ReadVIMovVX]>,
61916186
RISCVVPseudo;
61926187
let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VMV_S_X,
61936188
Constraints = "$rd = $rs1" in
61946189
def PseudoVMV_S_X # "_" # mx: Pseudo<(outs m.vrclass:$rd),
61956190
(ins m.vrclass:$rs1, GPR:$rs2,
61966191
AVL:$vl, ixlenimm:$sew),
61976192
[]>,
6198-
Sched<[WriteVIMovXV_MX, ReadVIMovXV_MX, ReadVIMovXX_MX]>,
6193+
Sched<[WriteVIMovXV, ReadVIMovXV, ReadVIMovXX]>,
61996194
RISCVVPseudo;
62006195
}
62016196
}
@@ -6211,17 +6206,12 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
62116206
foreach f = FPList in {
62126207
foreach m = f.MxList in {
62136208
defvar mx = m.MX;
6214-
defvar WriteVFMovVF_MX = !cast<SchedWrite>("WriteVFMovVF_" # mx);
6215-
defvar WriteVFMovFV_MX = !cast<SchedWrite>("WriteVFMovFV_" # mx);
6216-
defvar ReadVFMovVF_MX = !cast<SchedRead>("ReadVFMovVF_" # mx);
6217-
defvar ReadVFMovFV_MX = !cast<SchedRead>("ReadVFMovFV_" # mx);
6218-
defvar ReadVFMovFX_MX = !cast<SchedRead>("ReadVFMovFX_" # mx);
62196209
let VLMul = m.value in {
62206210
let HasSEWOp = 1, BaseInstr = VFMV_F_S in
62216211
def "PseudoVFMV_" # f.FX # "_S_" # mx :
62226212
Pseudo<(outs f.fprclass:$rd),
62236213
(ins m.vrclass:$rs2, ixlenimm:$sew), []>,
6224-
Sched<[WriteVFMovVF_MX, ReadVFMovVF_MX]>,
6214+
Sched<[WriteVFMovVF, ReadVFMovVF]>,
62256215
RISCVVPseudo;
62266216
let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VFMV_S_F,
62276217
Constraints = "$rd = $rs1" in
@@ -6230,7 +6220,7 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
62306220
(ins m.vrclass:$rs1, f.fprclass:$rs2,
62316221
AVL:$vl, ixlenimm:$sew),
62326222
[]>,
6233-
Sched<[WriteVFMovFV_MX, ReadVFMovFV_MX, ReadVFMovFX_MX]>,
6223+
Sched<[WriteVFMovFV, ReadVFMovFV, ReadVFMovFX]>,
62346224
RISCVVPseudo;
62356225
}
62366226
}

‎llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

Lines changed: 12 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -641,14 +641,16 @@ foreach mx = SchedMxList in {
641641
}
642642

643643
// 16. Vector Permutation Instructions
644+
let Latency = 8, ResourceCycles = [1] in {
645+
def : WriteRes<WriteVIMovVX, [SiFive7VA]>;
646+
def : WriteRes<WriteVIMovXV, [SiFive7VA]>;
647+
def : WriteRes<WriteVFMovVF, [SiFive7VA]>;
648+
def : WriteRes<WriteVFMovFV, [SiFive7VA]>;
649+
}
644650
foreach mx = SchedMxList in {
645651
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
646652
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
647653
let Latency = 8, ResourceCycles = [Cycles] in {
648-
defm "" : LMULWriteResMX<"WriteVIMovVX", [SiFive7VA], mx, IsWorstCase>;
649-
defm "" : LMULWriteResMX<"WriteVIMovXV", [SiFive7VA], mx, IsWorstCase>;
650-
defm "" : LMULWriteResMX<"WriteVFMovVF", [SiFive7VA], mx, IsWorstCase>;
651-
defm "" : LMULWriteResMX<"WriteVFMovFV", [SiFive7VA], mx, IsWorstCase>;
652654
defm "" : LMULWriteResMX<"WriteVRGatherVX", [SiFive7VA], mx, IsWorstCase>;
653655
defm "" : LMULWriteResMX<"WriteVRGatherVI", [SiFive7VA], mx, IsWorstCase>;
654656
}
@@ -929,12 +931,12 @@ defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;
929931
defm "" : LMULReadAdvance<"ReadVMIotV", 0>;
930932

931933
// 17. Vector Permutation Instructions
932-
defm "" : LMULReadAdvance<"ReadVIMovVX", 0>;
933-
defm "" : LMULReadAdvance<"ReadVIMovXV", 0>;
934-
defm "" : LMULReadAdvance<"ReadVIMovXX", 0>;
935-
defm "" : LMULReadAdvance<"ReadVFMovVF", 0>;
936-
defm "" : LMULReadAdvance<"ReadVFMovFV", 0>;
937-
defm "" : LMULReadAdvance<"ReadVFMovFX", 0>;
934+
def : ReadAdvance<ReadVIMovVX, 0>;
935+
def : ReadAdvance<ReadVIMovXV, 0>;
936+
def : ReadAdvance<ReadVIMovXX, 0>;
937+
def : ReadAdvance<ReadVFMovVF, 0>;
938+
def : ReadAdvance<ReadVFMovFV, 0>;
939+
def : ReadAdvance<ReadVFMovFX, 0>;
938940
defm "" : LMULReadAdvance<"ReadVISlideV", 0>;
939941
defm "" : LMULReadAdvance<"ReadVISlideX", 0>;
940942
defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;

‎llvm/lib/Target/RISCV/RISCVScheduleV.td

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -417,11 +417,11 @@ defm "" : LMULSchedWrites<"WriteVMIdxV">;
417417

418418
// 16. Vector Permutation Instructions
419419
// 16.1. Integer Scalar Move Instructions
420-
defm "" : LMULSchedWrites<"WriteVIMovVX">;
421-
defm "" : LMULSchedWrites<"WriteVIMovXV">;
420+
def WriteVIMovVX : SchedWrite;
421+
def WriteVIMovXV : SchedWrite;
422422
// 16.2. Floating-Point Scalar Move Instructions
423-
defm "" : LMULSchedWrites<"WriteVFMovVF">;
424-
defm "" : LMULSchedWrites<"WriteVFMovFV">;
423+
def WriteVFMovVF : SchedWrite;
424+
def WriteVFMovFV : SchedWrite;
425425
// 16.3. Vector Slide Instructions
426426
defm "" : LMULSchedWrites<"WriteVISlideX">;
427427
defm "" : LMULSchedWrites<"WriteVISlideI">;
@@ -637,13 +637,13 @@ defm "" : LMULSchedReads<"ReadVMIotV">;
637637

638638
// 16. Vector Permutation Instructions
639639
// 16.1. Integer Scalar Move Instructions
640-
defm "" : LMULSchedReads<"ReadVIMovVX">;
641-
defm "" : LMULSchedReads<"ReadVIMovXV">;
642-
defm "" : LMULSchedReads<"ReadVIMovXX">;
640+
def ReadVIMovVX : SchedRead;
641+
def ReadVIMovXV : SchedRead;
642+
def ReadVIMovXX : SchedRead;
643643
// 16.2. Floating-Point Scalar Move Instructions
644-
defm "" : LMULSchedReads<"ReadVFMovVF">;
645-
defm "" : LMULSchedReads<"ReadVFMovFV">;
646-
defm "" : LMULSchedReads<"ReadVFMovFX">;
644+
def ReadVFMovVF : SchedRead;
645+
def ReadVFMovFV : SchedRead;
646+
def ReadVFMovFX : SchedRead;
647647
// 16.3. Vector Slide Instructions
648648
defm "" : LMULSchedReads<"ReadVISlideV">;
649649
defm "" : LMULSchedReads<"ReadVISlideX">;
@@ -837,10 +837,10 @@ defm "" : LMULWriteRes<"WriteVMIotV", []>;
837837
defm "" : LMULWriteRes<"WriteVMIdxV", []>;
838838

839839
// 16. Vector Permutation Instructions
840-
defm "" : LMULWriteRes<"WriteVIMovVX", []>;
841-
defm "" : LMULWriteRes<"WriteVIMovXV", []>;
842-
defm "" : LMULWriteRes<"WriteVFMovVF", []>;
843-
defm "" : LMULWriteRes<"WriteVFMovFV", []>;
840+
def : WriteRes<WriteVIMovVX, []>;
841+
def : WriteRes<WriteVIMovXV, []>;
842+
def : WriteRes<WriteVFMovVF, []>;
843+
def : WriteRes<WriteVFMovFV, []>;
844844
defm "" : LMULWriteRes<"WriteVISlideX", []>;
845845
defm "" : LMULWriteRes<"WriteVISlideI", []>;
846846
defm "" : LMULWriteRes<"WriteVISlide1X", []>;
@@ -993,12 +993,12 @@ defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;
993993
defm "" : LMULReadAdvance<"ReadVMIotV", 0>;
994994

995995
// 16. Vector Permutation Instructions
996-
defm "" : LMULReadAdvance<"ReadVIMovVX", 0>;
997-
defm "" : LMULReadAdvance<"ReadVIMovXV", 0>;
998-
defm "" : LMULReadAdvance<"ReadVIMovXX", 0>;
999-
defm "" : LMULReadAdvance<"ReadVFMovVF", 0>;
1000-
defm "" : LMULReadAdvance<"ReadVFMovFV", 0>;
1001-
defm "" : LMULReadAdvance<"ReadVFMovFX", 0>;
996+
def : ReadAdvance<ReadVIMovVX, 0>;
997+
def : ReadAdvance<ReadVIMovXV, 0>;
998+
def : ReadAdvance<ReadVIMovXX, 0>;
999+
def : ReadAdvance<ReadVFMovVF, 0>;
1000+
def : ReadAdvance<ReadVFMovFV, 0>;
1001+
def : ReadAdvance<ReadVFMovFX, 0>;
10021002
defm "" : LMULReadAdvance<"ReadVISlideV", 0>;
10031003
defm "" : LMULReadAdvance<"ReadVISlideX", 0>;
10041004
defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;

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