[DAG] SimplifyDemandedBits - if we're only demanding the msb, a UMIN/UMAX node can be simplified to a AND/OR node respectively.

Alive2: https://alive2.llvm.org/ce/z/qnvmc6

Author: RKSimon

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

@@ -2152,9 +2152,12 @@ bool TargetLowering::SimplifyDemandedBits(
     break;
   }
   case ISD::UMIN: {
-    // Check if one arg is always less than (or equal) to the other arg.
     SDValue Op0 = Op.getOperand(0);
     SDValue Op1 = Op.getOperand(1);
+    // If we're only wanting the msb, then we can simplify to AND node.
+    if (OriginalDemandedBits.isSignMask())
+      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, Op0, Op1));
+    // Check if one arg is always less than (or equal) to the other arg.
     KnownBits Known0 = TLO.DAG.computeKnownBits(Op0, DemandedElts, Depth + 1);
     KnownBits Known1 = TLO.DAG.computeKnownBits(Op1, DemandedElts, Depth + 1);
     Known = KnownBits::umin(Known0, Known1);
@@ -2165,9 +2168,12 @@ bool TargetLowering::SimplifyDemandedBits(
     break;
   }
   case ISD::UMAX: {
-    // Check if one arg is always greater than (or equal) to the other arg.
     SDValue Op0 = Op.getOperand(0);
     SDValue Op1 = Op.getOperand(1);
+    // If we're only wanting the msb, then we can simplify to OR node.
+    if (OriginalDemandedBits.isSignMask())
+      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, VT, Op0, Op1));
+    // Check if one arg is always greater than (or equal) to the other arg.
     KnownBits Known0 = TLO.DAG.computeKnownBits(Op0, DemandedElts, Depth + 1);
     KnownBits Known1 = TLO.DAG.computeKnownBits(Op1, DemandedElts, Depth + 1);
     Known = KnownBits::umax(Known0, Known1);

llvm/test/CodeGen/VE/Scalar/umax.ll

@@ -28,8 +28,7 @@
 define zeroext i1 @func_umax_var_i1(i1 noundef zeroext %0, i1 noundef zeroext %1) {
 ; CHECK-LABEL: func_umax_var_i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    maxs.w.sx %s0, %s0, %s1
-; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT:    or %s0, %s0, %s1
 ; CHECK-NEXT:    b.l.t (, %s10)
   %3 = tail call i1 @llvm.umax.i1(i1 %0, i1 %1)
   ret i1 %3

llvm/test/CodeGen/VE/Scalar/umin.ll

@@ -28,8 +28,7 @@
 define zeroext i1 @func_umin_var_i1(i1 noundef zeroext %0, i1 noundef zeroext %1) {
 ; CHECK-LABEL: func_umin_var_i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    mins.w.sx %s0, %s0, %s1
-; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT:    and %s0, %s0, %s1
 ; CHECK-NEXT:    b.l.t (, %s10)
   %3 = tail call i1 @llvm.umin.i1(i1 %0, i1 %1)
   ret i1 %3

llvm/test/CodeGen/X86/umax.ll

@@ -1287,9 +1287,7 @@ define i64 @test_signbits_i64(i64 %a, i64 %b) nounwind {
 ; X86-LABEL: test_signbits_i64:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT:    cmpl %eax, %ecx
-; X86-NEXT:    cmoval %ecx, %eax
+; X86-NEXT:    orl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl %eax, %edx
 ; X86-NEXT:    sarl $31, %edx
 ; X86-NEXT:    retl
@@ -1304,8 +1302,7 @@ define i128 @test_signbits_i128(i128 %a, i128 %b) nounwind {
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rcx, %rax
 ; X64-NEXT:    sarq $28, %rax
-; X64-NEXT:    cmpq %rax, %rsi
-; X64-NEXT:    cmovaq %rsi, %rax
+; X64-NEXT:    orq %rsi, %rax
 ; X64-NEXT:    movq %rax, %rdx
 ; X64-NEXT:    sarq $63, %rdx
 ; X64-NEXT:    retq

llvm/test/CodeGen/X86/umin.ll

@@ -702,9 +702,7 @@ define i64 @test_signbits_i64(i64 %a, i64 %b) nounwind {
 ; X86-LABEL: test_signbits_i64:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT:    cmpl %eax, %ecx
-; X86-NEXT:    cmovbl %ecx, %eax
+; X86-NEXT:    andl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl %eax, %edx
 ; X86-NEXT:    sarl $31, %edx
 ; X86-NEXT:    retl
@@ -719,8 +717,7 @@ define i128 @test_signbits_i128(i128 %a, i128 %b) nounwind {
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rcx, %rax
 ; X64-NEXT:    sarq $28, %rax
-; X64-NEXT:    cmpq %rax, %rsi
-; X64-NEXT:    cmovbq %rsi, %rax
+; X64-NEXT:    andq %rsi, %rax
 ; X64-NEXT:    movq %rax, %rdx
 ; X64-NEXT:    sarq $63, %rdx
 ; X64-NEXT:    retq