Skip to content

Commit 5b07059

Browse files
asbasb
committed
[RISCV] Slightly weaken expanded seq_cst atomic op to match reference mapping in in the spec
Table A.6 in the RISC-V ISA Manual indicates that sequentially consistent atomic ops that have a matching instruction should be mapped to `amo<op>.{w|d}.aqrl`. But sequentially consistent operations that are mapped to lr/sc should produce `loop: lr.{w|d}.aqrl; <op>; sc.{w|d}.rl; bnez loop`. Previously, LLVM produced an `sc.{w|d}.aqrl` which was stronger than necessary. This patch adjusts the relevant logic so that a `sc.{w|d}.rl` is produced. Differential Revision: https://reviews.llvm.org/D146933
1 parent d03d98b commit 5b07059

File tree

6 files changed

+80
-80
lines changed

6 files changed

+80
-80
lines changed

‎llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -178,7 +178,7 @@ static unsigned getSCForRMW32(AtomicOrdering Ordering) {
178178
case AtomicOrdering::AcquireRelease:
179179
return RISCV::SC_W_RL;
180180
case AtomicOrdering::SequentiallyConsistent:
181-
return RISCV::SC_W_AQ_RL;
181+
return RISCV::SC_W_RL;
182182
}
183183
}
184184

@@ -212,7 +212,7 @@ static unsigned getSCForRMW64(AtomicOrdering Ordering) {
212212
case AtomicOrdering::AcquireRelease:
213213
return RISCV::SC_D_RL;
214214
case AtomicOrdering::SequentiallyConsistent:
215-
return RISCV::SC_D_AQ_RL;
215+
return RISCV::SC_D_RL;
216216
}
217217
}
218218

‎llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ define void @cmpxchg_and_branch1(ptr %ptr, i32 signext %cmp, i32 signext %val) n
2020
; CHECK-NEXT: bne a3, a1, .LBB0_1
2121
; CHECK-NEXT: # %bb.4: # %do_cmpxchg
2222
; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=2
23-
; CHECK-NEXT: sc.w.aqrl a4, a2, (a0)
23+
; CHECK-NEXT: sc.w.rl a4, a2, (a0)
2424
; CHECK-NEXT: bnez a4, .LBB0_3
2525
; CHECK-NEXT: # %bb.5: # %do_cmpxchg
2626
; CHECK-NEXT: # %bb.2: # %exit
@@ -48,7 +48,7 @@ define void @cmpxchg_and_branch2(ptr %ptr, i32 signext %cmp, i32 signext %val) n
4848
; CHECK-NEXT: bne a3, a1, .LBB1_5
4949
; CHECK-NEXT: # %bb.4: # %do_cmpxchg
5050
; CHECK-NEXT: # in Loop: Header=BB1_3 Depth=2
51-
; CHECK-NEXT: sc.w.aqrl a4, a2, (a0)
51+
; CHECK-NEXT: sc.w.rl a4, a2, (a0)
5252
; CHECK-NEXT: bnez a4, .LBB1_3
5353
; CHECK-NEXT: .LBB1_5: # %do_cmpxchg
5454
; CHECK-NEXT: # in Loop: Header=BB1_1 Depth=1
@@ -90,7 +90,7 @@ define void @cmpxchg_masked_and_branch1(ptr %ptr, i8 signext %cmp, i8 signext %v
9090
; RV32IA-NEXT: xor a5, a4, a2
9191
; RV32IA-NEXT: and a5, a5, a0
9292
; RV32IA-NEXT: xor a5, a4, a5
93-
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a3)
93+
; RV32IA-NEXT: sc.w.rl a5, a5, (a3)
9494
; RV32IA-NEXT: bnez a5, .LBB2_3
9595
; RV32IA-NEXT: # %bb.5: # %do_cmpxchg
9696
; RV32IA-NEXT: # %bb.2: # %exit
@@ -120,7 +120,7 @@ define void @cmpxchg_masked_and_branch1(ptr %ptr, i8 signext %cmp, i8 signext %v
120120
; RV64IA-NEXT: xor a5, a4, a2
121121
; RV64IA-NEXT: and a5, a5, a0
122122
; RV64IA-NEXT: xor a5, a4, a5
123-
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a3)
123+
; RV64IA-NEXT: sc.w.rl a5, a5, (a3)
124124
; RV64IA-NEXT: bnez a5, .LBB2_3
125125
; RV64IA-NEXT: # %bb.5: # %do_cmpxchg
126126
; RV64IA-NEXT: # %bb.2: # %exit
@@ -160,7 +160,7 @@ define void @cmpxchg_masked_and_branch2(ptr %ptr, i8 signext %cmp, i8 signext %v
160160
; RV32IA-NEXT: xor a5, a4, a2
161161
; RV32IA-NEXT: and a5, a5, a0
162162
; RV32IA-NEXT: xor a5, a4, a5
163-
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a3)
163+
; RV32IA-NEXT: sc.w.rl a5, a5, (a3)
164164
; RV32IA-NEXT: bnez a5, .LBB3_3
165165
; RV32IA-NEXT: .LBB3_5: # %do_cmpxchg
166166
; RV32IA-NEXT: # in Loop: Header=BB3_1 Depth=1
@@ -193,7 +193,7 @@ define void @cmpxchg_masked_and_branch2(ptr %ptr, i8 signext %cmp, i8 signext %v
193193
; RV64IA-NEXT: xor a5, a4, a2
194194
; RV64IA-NEXT: and a5, a5, a0
195195
; RV64IA-NEXT: xor a5, a4, a5
196-
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a3)
196+
; RV64IA-NEXT: sc.w.rl a5, a5, (a3)
197197
; RV64IA-NEXT: bnez a5, .LBB3_3
198198
; RV64IA-NEXT: .LBB3_5: # %do_cmpxchg
199199
; RV64IA-NEXT: # in Loop: Header=BB3_1 Depth=1
@@ -224,7 +224,7 @@ define void @cmpxchg_and_irrelevant_branch(ptr %ptr, i32 signext %cmp, i32 signe
224224
; CHECK-NEXT: bne a4, a1, .LBB4_5
225225
; CHECK-NEXT: # %bb.4: # %do_cmpxchg
226226
; CHECK-NEXT: # in Loop: Header=BB4_3 Depth=2
227-
; CHECK-NEXT: sc.w.aqrl a5, a2, (a0)
227+
; CHECK-NEXT: sc.w.rl a5, a2, (a0)
228228
; CHECK-NEXT: bnez a5, .LBB4_3
229229
; CHECK-NEXT: .LBB4_5: # %do_cmpxchg
230230
; CHECK-NEXT: # in Loop: Header=BB4_1 Depth=1

‎llvm/test/CodeGen/RISCV/atomic-cmpxchg-flag.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ define i1 @cmpxchg_i32_seq_cst_seq_cst(ptr %ptr, i32 signext %cmp,
1515
; RV64IA-NEXT: bne a3, a1, .LBB0_3
1616
; RV64IA-NEXT: # %bb.2: # %entry
1717
; RV64IA-NEXT: # in Loop: Header=BB0_1 Depth=1
18-
; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0)
18+
; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
1919
; RV64IA-NEXT: bnez a4, .LBB0_1
2020
; RV64IA-NEXT: .LBB0_3: # %entry
2121
; RV64IA-NEXT: xor a1, a3, a1

‎llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll

Lines changed: 21 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -576,7 +576,7 @@ define void @cmpxchg_i8_seq_cst_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
576576
; RV32IA-NEXT: xor a5, a2, a0
577577
; RV32IA-NEXT: and a5, a5, a4
578578
; RV32IA-NEXT: xor a5, a2, a5
579-
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a3)
579+
; RV32IA-NEXT: sc.w.rl a5, a5, (a3)
580580
; RV32IA-NEXT: bnez a5, .LBB7_1
581581
; RV32IA-NEXT: .LBB7_3:
582582
; RV32IA-NEXT: ret
@@ -612,7 +612,7 @@ define void @cmpxchg_i8_seq_cst_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
612612
; RV64IA-NEXT: xor a5, a2, a0
613613
; RV64IA-NEXT: and a5, a5, a4
614614
; RV64IA-NEXT: xor a5, a2, a5
615-
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a3)
615+
; RV64IA-NEXT: sc.w.rl a5, a5, (a3)
616616
; RV64IA-NEXT: bnez a5, .LBB7_1
617617
; RV64IA-NEXT: .LBB7_3:
618618
; RV64IA-NEXT: ret
@@ -652,7 +652,7 @@ define void @cmpxchg_i8_seq_cst_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind {
652652
; RV32IA-NEXT: xor a5, a2, a0
653653
; RV32IA-NEXT: and a5, a5, a4
654654
; RV32IA-NEXT: xor a5, a2, a5
655-
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a3)
655+
; RV32IA-NEXT: sc.w.rl a5, a5, (a3)
656656
; RV32IA-NEXT: bnez a5, .LBB8_1
657657
; RV32IA-NEXT: .LBB8_3:
658658
; RV32IA-NEXT: ret
@@ -688,7 +688,7 @@ define void @cmpxchg_i8_seq_cst_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind {
688688
; RV64IA-NEXT: xor a5, a2, a0
689689
; RV64IA-NEXT: and a5, a5, a4
690690
; RV64IA-NEXT: xor a5, a2, a5
691-
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a3)
691+
; RV64IA-NEXT: sc.w.rl a5, a5, (a3)
692692
; RV64IA-NEXT: bnez a5, .LBB8_1
693693
; RV64IA-NEXT: .LBB8_3:
694694
; RV64IA-NEXT: ret
@@ -728,7 +728,7 @@ define void @cmpxchg_i8_seq_cst_seq_cst(ptr %ptr, i8 %cmp, i8 %val) nounwind {
728728
; RV32IA-NEXT: xor a5, a2, a0
729729
; RV32IA-NEXT: and a5, a5, a4
730730
; RV32IA-NEXT: xor a5, a2, a5
731-
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a3)
731+
; RV32IA-NEXT: sc.w.rl a5, a5, (a3)
732732
; RV32IA-NEXT: bnez a5, .LBB9_1
733733
; RV32IA-NEXT: .LBB9_3:
734734
; RV32IA-NEXT: ret
@@ -764,7 +764,7 @@ define void @cmpxchg_i8_seq_cst_seq_cst(ptr %ptr, i8 %cmp, i8 %val) nounwind {
764764
; RV64IA-NEXT: xor a5, a2, a0
765765
; RV64IA-NEXT: and a5, a5, a4
766766
; RV64IA-NEXT: xor a5, a2, a5
767-
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a3)
767+
; RV64IA-NEXT: sc.w.rl a5, a5, (a3)
768768
; RV64IA-NEXT: bnez a5, .LBB9_1
769769
; RV64IA-NEXT: .LBB9_3:
770770
; RV64IA-NEXT: ret
@@ -1351,7 +1351,7 @@ define void @cmpxchg_i16_seq_cst_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
13511351
; RV32IA-NEXT: xor a4, a2, a0
13521352
; RV32IA-NEXT: and a4, a4, a5
13531353
; RV32IA-NEXT: xor a4, a2, a4
1354-
; RV32IA-NEXT: sc.w.aqrl a4, a4, (a3)
1354+
; RV32IA-NEXT: sc.w.rl a4, a4, (a3)
13551355
; RV32IA-NEXT: bnez a4, .LBB17_1
13561356
; RV32IA-NEXT: .LBB17_3:
13571357
; RV32IA-NEXT: ret
@@ -1388,7 +1388,7 @@ define void @cmpxchg_i16_seq_cst_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
13881388
; RV64IA-NEXT: xor a4, a2, a0
13891389
; RV64IA-NEXT: and a4, a4, a5
13901390
; RV64IA-NEXT: xor a4, a2, a4
1391-
; RV64IA-NEXT: sc.w.aqrl a4, a4, (a3)
1391+
; RV64IA-NEXT: sc.w.rl a4, a4, (a3)
13921392
; RV64IA-NEXT: bnez a4, .LBB17_1
13931393
; RV64IA-NEXT: .LBB17_3:
13941394
; RV64IA-NEXT: ret
@@ -1429,7 +1429,7 @@ define void @cmpxchg_i16_seq_cst_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
14291429
; RV32IA-NEXT: xor a4, a2, a0
14301430
; RV32IA-NEXT: and a4, a4, a5
14311431
; RV32IA-NEXT: xor a4, a2, a4
1432-
; RV32IA-NEXT: sc.w.aqrl a4, a4, (a3)
1432+
; RV32IA-NEXT: sc.w.rl a4, a4, (a3)
14331433
; RV32IA-NEXT: bnez a4, .LBB18_1
14341434
; RV32IA-NEXT: .LBB18_3:
14351435
; RV32IA-NEXT: ret
@@ -1466,7 +1466,7 @@ define void @cmpxchg_i16_seq_cst_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
14661466
; RV64IA-NEXT: xor a4, a2, a0
14671467
; RV64IA-NEXT: and a4, a4, a5
14681468
; RV64IA-NEXT: xor a4, a2, a4
1469-
; RV64IA-NEXT: sc.w.aqrl a4, a4, (a3)
1469+
; RV64IA-NEXT: sc.w.rl a4, a4, (a3)
14701470
; RV64IA-NEXT: bnez a4, .LBB18_1
14711471
; RV64IA-NEXT: .LBB18_3:
14721472
; RV64IA-NEXT: ret
@@ -1507,7 +1507,7 @@ define void @cmpxchg_i16_seq_cst_seq_cst(ptr %ptr, i16 %cmp, i16 %val) nounwind
15071507
; RV32IA-NEXT: xor a4, a2, a0
15081508
; RV32IA-NEXT: and a4, a4, a5
15091509
; RV32IA-NEXT: xor a4, a2, a4
1510-
; RV32IA-NEXT: sc.w.aqrl a4, a4, (a3)
1510+
; RV32IA-NEXT: sc.w.rl a4, a4, (a3)
15111511
; RV32IA-NEXT: bnez a4, .LBB19_1
15121512
; RV32IA-NEXT: .LBB19_3:
15131513
; RV32IA-NEXT: ret
@@ -1544,7 +1544,7 @@ define void @cmpxchg_i16_seq_cst_seq_cst(ptr %ptr, i16 %cmp, i16 %val) nounwind
15441544
; RV64IA-NEXT: xor a4, a2, a0
15451545
; RV64IA-NEXT: and a4, a4, a5
15461546
; RV64IA-NEXT: xor a4, a2, a4
1547-
; RV64IA-NEXT: sc.w.aqrl a4, a4, (a3)
1547+
; RV64IA-NEXT: sc.w.rl a4, a4, (a3)
15481548
; RV64IA-NEXT: bnez a4, .LBB19_1
15491549
; RV64IA-NEXT: .LBB19_3:
15501550
; RV64IA-NEXT: ret
@@ -1943,7 +1943,7 @@ define void @cmpxchg_i32_seq_cst_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
19431943
; RV32IA-NEXT: lr.w.aqrl a3, (a0)
19441944
; RV32IA-NEXT: bne a3, a1, .LBB27_3
19451945
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1
1946-
; RV32IA-NEXT: sc.w.aqrl a4, a2, (a0)
1946+
; RV32IA-NEXT: sc.w.rl a4, a2, (a0)
19471947
; RV32IA-NEXT: bnez a4, .LBB27_1
19481948
; RV32IA-NEXT: .LBB27_3:
19491949
; RV32IA-NEXT: ret
@@ -1968,7 +1968,7 @@ define void @cmpxchg_i32_seq_cst_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
19681968
; RV64IA-NEXT: lr.w.aqrl a3, (a0)
19691969
; RV64IA-NEXT: bne a3, a1, .LBB27_3
19701970
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1
1971-
; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0)
1971+
; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
19721972
; RV64IA-NEXT: bnez a4, .LBB27_1
19731973
; RV64IA-NEXT: .LBB27_3:
19741974
; RV64IA-NEXT: ret
@@ -1996,7 +1996,7 @@ define void @cmpxchg_i32_seq_cst_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
19961996
; RV32IA-NEXT: lr.w.aqrl a3, (a0)
19971997
; RV32IA-NEXT: bne a3, a1, .LBB28_3
19981998
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1
1999-
; RV32IA-NEXT: sc.w.aqrl a4, a2, (a0)
1999+
; RV32IA-NEXT: sc.w.rl a4, a2, (a0)
20002000
; RV32IA-NEXT: bnez a4, .LBB28_1
20012001
; RV32IA-NEXT: .LBB28_3:
20022002
; RV32IA-NEXT: ret
@@ -2021,7 +2021,7 @@ define void @cmpxchg_i32_seq_cst_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
20212021
; RV64IA-NEXT: lr.w.aqrl a3, (a0)
20222022
; RV64IA-NEXT: bne a3, a1, .LBB28_3
20232023
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1
2024-
; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0)
2024+
; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
20252025
; RV64IA-NEXT: bnez a4, .LBB28_1
20262026
; RV64IA-NEXT: .LBB28_3:
20272027
; RV64IA-NEXT: ret
@@ -2049,7 +2049,7 @@ define void @cmpxchg_i32_seq_cst_seq_cst(ptr %ptr, i32 %cmp, i32 %val) nounwind
20492049
; RV32IA-NEXT: lr.w.aqrl a3, (a0)
20502050
; RV32IA-NEXT: bne a3, a1, .LBB29_3
20512051
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1
2052-
; RV32IA-NEXT: sc.w.aqrl a4, a2, (a0)
2052+
; RV32IA-NEXT: sc.w.rl a4, a2, (a0)
20532053
; RV32IA-NEXT: bnez a4, .LBB29_1
20542054
; RV32IA-NEXT: .LBB29_3:
20552055
; RV32IA-NEXT: ret
@@ -2074,7 +2074,7 @@ define void @cmpxchg_i32_seq_cst_seq_cst(ptr %ptr, i32 %cmp, i32 %val) nounwind
20742074
; RV64IA-NEXT: lr.w.aqrl a3, (a0)
20752075
; RV64IA-NEXT: bne a3, a1, .LBB29_3
20762076
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1
2077-
; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0)
2077+
; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
20782078
; RV64IA-NEXT: bnez a4, .LBB29_1
20792079
; RV64IA-NEXT: .LBB29_3:
20802080
; RV64IA-NEXT: ret
@@ -2568,7 +2568,7 @@ define void @cmpxchg_i64_seq_cst_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin
25682568
; RV64IA-NEXT: lr.d.aqrl a3, (a0)
25692569
; RV64IA-NEXT: bne a3, a1, .LBB37_3
25702570
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB37_1 Depth=1
2571-
; RV64IA-NEXT: sc.d.aqrl a4, a2, (a0)
2571+
; RV64IA-NEXT: sc.d.rl a4, a2, (a0)
25722572
; RV64IA-NEXT: bnez a4, .LBB37_1
25732573
; RV64IA-NEXT: .LBB37_3:
25742574
; RV64IA-NEXT: ret
@@ -2630,7 +2630,7 @@ define void @cmpxchg_i64_seq_cst_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind
26302630
; RV64IA-NEXT: lr.d.aqrl a3, (a0)
26312631
; RV64IA-NEXT: bne a3, a1, .LBB38_3
26322632
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB38_1 Depth=1
2633-
; RV64IA-NEXT: sc.d.aqrl a4, a2, (a0)
2633+
; RV64IA-NEXT: sc.d.rl a4, a2, (a0)
26342634
; RV64IA-NEXT: bnez a4, .LBB38_1
26352635
; RV64IA-NEXT: .LBB38_3:
26362636
; RV64IA-NEXT: ret
@@ -2692,7 +2692,7 @@ define void @cmpxchg_i64_seq_cst_seq_cst(ptr %ptr, i64 %cmp, i64 %val) nounwind
26922692
; RV64IA-NEXT: lr.d.aqrl a3, (a0)
26932693
; RV64IA-NEXT: bne a3, a1, .LBB39_3
26942694
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1
2695-
; RV64IA-NEXT: sc.d.aqrl a4, a2, (a0)
2695+
; RV64IA-NEXT: sc.d.rl a4, a2, (a0)
26962696
; RV64IA-NEXT: bnez a4, .LBB39_1
26972697
; RV64IA-NEXT: .LBB39_3:
26982698
; RV64IA-NEXT: ret

0 commit comments

Comments
 (0)