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Francesco Petrogalli
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[MC][SVE] Fix data operand for instruction alias of st1d.
The version of `st1d` that operates with vector plus immediate addressing mode uses the alias `st1d { <Zn>.d }, <Pg>, [<Za>.d]` for rendering `st1d { <Zn>.d }, <Pg>, [<Za>.d, #0]`. The disassembler was generating `<Zn>.s` instead of `<Zn>.d>`. Differential Revision: https://reviews.llvm.org/D86633
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‎llvm/lib/Target/AArch64/SVEInstrFormats.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5487,7 +5487,7 @@ multiclass sve_mem_64b_sst_vi_ptrs<bits<3> opc, string asm,
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def : InstAlias<asm # "\t$Zt, $Pg, [$Zn, $imm5]",
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(!cast<Instruction>(NAME # _IMM) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), 0>;
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def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
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(!cast<Instruction>(NAME # _IMM) Z_s:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
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(!cast<Instruction>(NAME # _IMM) Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
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def : Pat<(op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), (nxv2i64 ZPR:$ptrs), imm_ty:$index, vt),
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(!cast<Instruction>(NAME # _IMM) ZPR:$data, PPR:$gp, ZPR:$ptrs, imm_ty:$index)>;

‎llvm/test/MC/AArch64/SVE/st1b.s

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -168,3 +168,27 @@ st1b { z31.d }, p7, [z31.d, #31]
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// CHECK-ENCODING: [0xff,0xbf,0x5f,0xe4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff bf 5f e4 <unknown>
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st1b { z0.s }, p7, [z0.s, #0]
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// CHECK-INST: st1b { z0.s }, p7, [z0.s]
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// CHECK-ENCODING: [0x00,0xbc,0x60,0xe4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 bc 60 e4 <unknown>
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st1b { z0.s }, p7, [z0.s]
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// CHECK-INST: st1b { z0.s }, p7, [z0.s]
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// CHECK-ENCODING: [0x00,0xbc,0x60,0xe4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 bc 60 e4 <unknown>
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st1b { z0.d }, p7, [z0.d, #0]
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// CHECK-INST: st1b { z0.d }, p7, [z0.d]
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// CHECK-ENCODING: [0x00,0xbc,0x40,0xe4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 bc 40 e4 <unknown>
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st1b { z0.d }, p7, [z0.d]
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// CHECK-INST: st1b { z0.d }, p7, [z0.d]
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// CHECK-ENCODING: [0x00,0xbc,0x40,0xe4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 bc 40 e4 <unknown>

‎llvm/test/MC/AArch64/SVE/st1d.s

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -78,3 +78,15 @@ st1d { z31.d }, p7, [z31.d, #248]
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// CHECK-ENCODING: [0xff,0xbf,0xdf,0xe5]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff bf df e5 <unknown>
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st1d { z0.d }, p7, [z0.d, #0]
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// CHECK-INST: st1d { z0.d }, p7, [z0.d]
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// CHECK-ENCODING: [0x00,0xbc,0xc0,0xe5]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 bc c0 e5 <unknown>
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st1d { z0.d }, p7, [z0.d]
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// CHECK-INST: st1d { z0.d }, p7, [z0.d]
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// CHECK-ENCODING: [0x00,0xbc,0xc0,0xe5]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 bc c0 e5 <unknown>

‎llvm/test/MC/AArch64/SVE/st1h.s

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -168,3 +168,27 @@ st1h { z31.d }, p7, [z31.d, #62]
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// CHECK-ENCODING: [0xff,0xbf,0xdf,0xe4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff bf df e4 <unknown>
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st1h { z0.s }, p7, [z0.s, #0]
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// CHECK-INST: st1h { z0.s }, p7, [z0.s]
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// CHECK-ENCODING: [0x00,0xbc,0xe0,0xe4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 bc e0 e4 <unknown>
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st1h { z0.s }, p7, [z0.s]
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// CHECK-INST: st1h { z0.s }, p7, [z0.s]
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// CHECK-ENCODING: [0x00,0xbc,0xe0,0xe4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 bc e0 e4 <unknown>
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st1h { z0.d }, p7, [z0.d, #0]
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// CHECK-INST: st1h { z0.d }, p7, [z0.d]
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// CHECK-ENCODING: [0x00,0xbc,0xc0,0xe4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 bc c0 e4 <unknown>
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st1h { z0.d }, p7, [z0.d]
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// CHECK-INST: st1h { z0.d }, p7, [z0.d]
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// CHECK-ENCODING: [0x00,0xbc,0xc0,0xe4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 bc c0 e4 <unknown>

‎llvm/test/MC/AArch64/SVE/st1w.s

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -138,3 +138,27 @@ st1w { z31.d }, p7, [z31.d, #124]
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// CHECK-ENCODING: [0xff,0xbf,0x5f,0xe5]
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// CHECK-ERROR: instruction requires: sve
140140
// CHECK-UNKNOWN: ff bf 5f e5 <unknown>
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st1w { z0.s }, p7, [z0.s, #0]
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// CHECK-INST: st1w { z0.s }, p7, [z0.s]
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// CHECK-ENCODING: [0x00,0xbc,0x60,0xe5]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 bc 60 e5 <unknown>
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st1w { z0.s }, p7, [z0.s]
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// CHECK-INST: st1w { z0.s }, p7, [z0.s]
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// CHECK-ENCODING: [0x00,0xbc,0x60,0xe5]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 bc 60 e5 <unknown>
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st1w { z0.d }, p7, [z0.d, #0]
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// CHECK-INST: st1w { z0.d }, p7, [z0.d]
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// CHECK-ENCODING: [0x00,0xbc,0x40,0xe5]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 bc 40 e5 <unknown>
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st1w { z0.d }, p7, [z0.d]
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// CHECK-INST: st1w { z0.d }, p7, [z0.d]
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// CHECK-ENCODING: [0x00,0xbc,0x40,0xe5]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 bc 40 e5 <unknown>

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