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[ARM] Make getInstSizeInBytes() use instruction size from InstrInfo.td
Currently, ARMBaseInstrInfo::getInstSizeInBytes() uses hard-coded instruction size for some pseudo-instructions, while this information should ideally be found in ARMInstrInfo.td, ARMInstrThumb(2).td files (which can be accessed via MCInstrDesc). Hence, the .td files should be updated and no hard-coded instruction sizes should be used by getInstSizeInBytes() anymore. Differential Revision: https://reviews.llvm.org/D118009
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7 files changed

+286
-44
lines changed

7 files changed

+286
-44
lines changed

‎llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

Lines changed: 6 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -752,23 +752,17 @@ unsigned ARMBaseInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
752752
const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
753753

754754
const MCInstrDesc &MCID = MI.getDesc();
755-
if (MCID.getSize())
756-
return MCID.getSize();
757755

758756
switch (MI.getOpcode()) {
759757
default:
760-
// pseudo-instruction sizes are zero.
761-
return 0;
758+
// Return the size specified in .td file. If there's none, return 0, as we
759+
// can't define a default size (Thumb1 instructions are 2 bytes, Thumb2
760+
// instructions are 2-4 bytes, and ARM instructions are 4 bytes), in
761+
// contrast to AArch64 instructions which have a default size of 4 bytes for
762+
// example.
763+
return MCID.getSize();
762764
case TargetOpcode::BUNDLE:
763765
return getInstBundleLength(MI);
764-
case ARM::MOVi16_ga_pcrel:
765-
case ARM::MOVTi16_ga_pcrel:
766-
case ARM::t2MOVi16_ga_pcrel:
767-
case ARM::t2MOVTi16_ga_pcrel:
768-
return 4;
769-
case ARM::MOVi32imm:
770-
case ARM::t2MOVi32imm:
771-
return 8;
772766
case ARM::CONSTPOOL_ENTRY:
773767
case ARM::JUMPTABLE_INSTS:
774768
case ARM::JUMPTABLE_ADDRS:
@@ -777,19 +771,6 @@ unsigned ARMBaseInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
777771
// If this machine instr is a constant pool entry, its size is recorded as
778772
// operand #2.
779773
return MI.getOperand(2).getImm();
780-
case ARM::Int_eh_sjlj_longjmp:
781-
return 16;
782-
case ARM::tInt_eh_sjlj_longjmp:
783-
return 10;
784-
case ARM::tInt_WIN_eh_sjlj_longjmp:
785-
return 12;
786-
case ARM::Int_eh_sjlj_setjmp:
787-
case ARM::Int_eh_sjlj_setjmp_nofp:
788-
return 20;
789-
case ARM::tInt_eh_sjlj_setjmp:
790-
case ARM::t2Int_eh_sjlj_setjmp:
791-
case ARM::t2Int_eh_sjlj_setjmp_nofp:
792-
return 12;
793774
case ARM::SPACE:
794775
return MI.getOperand(1).getImm();
795776
case ARM::INLINEASM:
@@ -800,14 +781,6 @@ unsigned ARMBaseInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
800781
Size = alignTo(Size, 4);
801782
return Size;
802783
}
803-
case ARM::SpeculationBarrierISBDSBEndBB:
804-
case ARM::t2SpeculationBarrierISBDSBEndBB:
805-
// This gets lowered to 2 4-byte instructions.
806-
return 8;
807-
case ARM::SpeculationBarrierSBEndBB:
808-
case ARM::t2SpeculationBarrierSBEndBB:
809-
// This gets lowered to 1 4-byte instructions.
810-
return 4;
811784
}
812785
}
813786

‎llvm/lib/Target/ARM/ARMInstrInfo.td

Lines changed: 15 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3657,6 +3657,8 @@ def : InstAlias<"mov${p} $Rd, $imm",
36573657
(MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p), 0>,
36583658
Requires<[IsARM, HasV6T2]>;
36593659

3660+
// This gets lowered to a single 4-byte instructions
3661+
let Size = 4 in
36603662
def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
36613663
(ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
36623664
Sched<[WriteALU]>;
@@ -3680,6 +3682,8 @@ def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
36803682
let DecoderMethod = "DecodeArmMOVTWInstruction";
36813683
}
36823684

3685+
// This gets lowered to a single 4-byte instructions
3686+
let Size = 4 in
36833687
def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
36843688
(ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
36853689
Sched<[WriteALU]>;
@@ -5895,27 +5899,30 @@ def : ARMPat<(ARMthread_pointer), (MRC 15, 0, 13, 0, 3)>,
58955899
//
58965900
// These are pseudo-instructions and are lowered to individual MC-insts, so
58975901
// no encoding information is necessary.
5902+
// This gets lowered to an instruction sequence of 20 bytes
58985903
let Defs =
58995904
[ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
59005905
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
5901-
hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5906+
hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1, Size = 20 in {
59025907
def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
59035908
NoItinerary,
59045909
[(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
59055910
Requires<[IsARM, HasVFP2]>;
59065911
}
59075912

5913+
// This gets lowered to an instruction sequence of 20 bytes
59085914
let Defs =
59095915
[ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
5910-
hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5916+
hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1, Size = 20 in {
59115917
def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
59125918
NoItinerary,
59135919
[(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
59145920
Requires<[IsARM, NoVFP]>;
59155921
}
59165922

5923+
// This gets lowered to an instruction sequence of 16 bytes
59175924
// FIXME: Non-IOS version(s)
5918-
let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
5925+
let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, Size = 16,
59195926
Defs = [ R7, LR, SP ] in {
59205927
def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
59215928
NoItinerary,
@@ -5958,7 +5965,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in
59585965
// This is a single pseudo instruction, the benefit is that it can be remat'd
59595966
// as a single unit instead of having to handle reg inputs.
59605967
// FIXME: Remove this when we can do generalized remat.
5961-
let isReMaterializable = 1, isMoveImm = 1 in
5968+
let isReMaterializable = 1, isMoveImm = 1, Size = 8 in
59625969
def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
59635970
[(set GPR:$dst, (arm_i32imm:$src))]>,
59645971
Requires<[IsARM]>;
@@ -6419,8 +6426,12 @@ def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn),
64196426
// SpeculationBarrierEndBB must only be used after an unconditional control
64206427
// flow, i.e. after a terminator for which isBarrier is True.
64216428
let hasSideEffects = 1, isCodeGenOnly = 1, isTerminator = 1, isBarrier = 1 in {
6429+
// This gets lowered to a pair of 4-byte instructions
6430+
let Size = 8 in
64226431
def SpeculationBarrierISBDSBEndBB
64236432
: PseudoInst<(outs), (ins), NoItinerary, []>, Sched<[]>;
6433+
// This gets lowered to a single 4-byte instructions
6434+
let Size = 4 in
64246435
def SpeculationBarrierSBEndBB
64256436
: PseudoInst<(outs), (ins), NoItinerary, []>, Sched<[]>;
64266437
}

‎llvm/lib/Target/ARM/ARMInstrThumb.td

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1537,25 +1537,28 @@ def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
15371537
// Defs. By doing so, we also cause the prologue/epilogue code to actively
15381538
// preserve all of the callee-saved registers, which is exactly what we want.
15391539
// $val is a scratch register for our use.
1540+
// This gets lowered to an instruction sequence of 12 bytes
15401541
let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1541-
hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
1542+
hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, Size = 12,
15421543
usesCustomInserter = 1 in
15431544
def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
15441545
AddrModeNone, 0, NoItinerary, "","",
15451546
[(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
15461547

1548+
// This gets lowered to an instruction sequence of 10 bytes
15471549
// FIXME: Non-IOS version(s)
15481550
let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1549-
Defs = [ R7, LR, SP ] in
1551+
Size = 10, Defs = [ R7, LR, SP ] in
15501552
def tInt_eh_sjlj_longjmp : XI<(outs), (ins tGPR:$src, tGPR:$scratch),
15511553
AddrModeNone, 0, IndexModeNone,
15521554
Pseudo, NoItinerary, "", "",
15531555
[(ARMeh_sjlj_longjmp tGPR:$src, tGPR:$scratch)]>,
15541556
Requires<[IsThumb,IsNotWindows]>;
15551557

1558+
// This gets lowered to an instruction sequence of 12 bytes
15561559
// (Windows is Thumb2-only)
15571560
let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1558-
Defs = [ R11, LR, SP ] in
1561+
Size = 12, Defs = [ R11, LR, SP ] in
15591562
def tInt_WIN_eh_sjlj_longjmp
15601563
: XI<(outs), (ins GPR:$src, GPR:$scratch), AddrModeNone, 0, IndexModeNone,
15611564
Pseudo, NoItinerary, "", "", [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,

‎llvm/lib/Target/ARM/ARMInstrThumb2.td

Lines changed: 13 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2194,6 +2194,8 @@ def : InstAlias<"mov${p} $Rd, $imm",
21942194
(t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p), 0>,
21952195
Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteALU]>;
21962196

2197+
// This gets lowered to a single 4-byte instructions
2198+
let Size = 4 in
21972199
def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
21982200
(ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
21992201
Sched<[WriteALU]>;
@@ -2223,6 +2225,8 @@ def t2MOVTi16 : T2I<(outs rGPR:$Rd),
22232225
let DecoderMethod = "DecodeT2MOVTWInstruction";
22242226
}
22252227

2228+
// This gets lowered to a single 4-byte instructions
2229+
let Size = 4 in
22262230
def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
22272231
(ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
22282232
Sched<[WriteALU]>, Requires<[IsThumb, HasV8MBaseline]>;
@@ -3814,20 +3818,22 @@ def : T2Pat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
38143818
// doing so, we also cause the prologue/epilogue code to actively preserve
38153819
// all of the callee-saved registers, which is exactly what we want.
38163820
// $val is a scratch register for our use.
3821+
// This gets lowered to an instruction sequence of 12 bytes
38173822
let Defs =
38183823
[ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
38193824
Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
3820-
hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3825+
hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, Size = 12,
38213826
usesCustomInserter = 1 in {
38223827
def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
38233828
AddrModeNone, 0, NoItinerary, "", "",
38243829
[(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
38253830
Requires<[IsThumb2, HasVFP2]>;
38263831
}
38273832

3833+
// This gets lowered to an instruction sequence of 12 bytes
38283834
let Defs =
38293835
[ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3830-
hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3836+
hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, Size = 12,
38313837
usesCustomInserter = 1 in {
38323838
def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
38333839
AddrModeNone, 0, NoItinerary, "", "",
@@ -4224,7 +4230,7 @@ def : t2InstAlias<"hvc\t$imm16", (t2HVC imm0_65535:$imm16)>;
42244230
// 32-bit immediate using movw + movt.
42254231
// This is a single pseudo instruction to make it re-materializable.
42264232
// FIXME: Remove this when we can do generalized remat.
4227-
let isReMaterializable = 1, isMoveImm = 1 in
4233+
let isReMaterializable = 1, isMoveImm = 1, Size = 8 in
42284234
def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
42294235
[(set rGPR:$dst, (i32 imm:$src))]>,
42304236
Requires<[IsThumb, UseMovt]>;
@@ -5006,8 +5012,12 @@ def : InstAlias<"dfb${p}", (t2DSB 0xc, pred:$p), 1>, Requires<[HasDFB]>;
50065012
// SpeculationBarrierEndBB must only be used after an unconditional control
50075013
// flow, i.e. after a terminator for which isBarrier is True.
50085014
let hasSideEffects = 1, isCodeGenOnly = 1, isTerminator = 1, isBarrier = 1 in {
5015+
// This gets lowered to a pair of 4-byte instructions
5016+
let Size = 8 in
50095017
def t2SpeculationBarrierISBDSBEndBB
50105018
: PseudoInst<(outs), (ins), NoItinerary, []>, Sched<[]>;
5019+
// This gets lowered to a single 4-byte instructions
5020+
let Size = 4 in
50115021
def t2SpeculationBarrierSBEndBB
50125022
: PseudoInst<(outs), (ins), NoItinerary, []>, Sched<[]>;
50135023
}

‎llvm/unittests/Target/ARM/CMakeLists.txt

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,11 +10,13 @@ set(LLVM_LINK_COMPONENTS
1010
CodeGen
1111
GlobalISel
1212
MC
13+
MIRParser
1314
SelectionDAG
1415
Support
1516
Target
1617
)
1718

1819
add_llvm_target_unittest(ARMTests
1920
MachineInstrTest.cpp
21+
InstSizes.cpp
2022
)

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