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6 | 6 | define i8 @widget(i8* %arr, i8 %t9) {
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7 | 7 | ; CHECK-LABEL: @widget(
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8 | 8 | ; CHECK-NEXT: bb:
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9 |
| -; CHECK-NEXT: [[ARR2:%.*]] = ptrtoint i8* [[ARR:%.*]] to i64 |
| 9 | +; CHECK-NEXT: [[ARR1:%.*]] = ptrtoint i8* [[ARR:%.*]] to i64 |
10 | 10 | ; CHECK-NEXT: br label [[BB6:%.*]]
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11 | 11 | ; CHECK: bb6:
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12 | 12 | ; CHECK-NEXT: [[T1_0:%.*]] = phi i8* [ [[ARR]], [[BB:%.*]] ], [ null, [[BB6]] ]
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13 | 13 | ; CHECK-NEXT: [[C:%.*]] = call i1 @cond()
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14 | 14 | ; CHECK-NEXT: br i1 [[C]], label [[FOR_PREHEADER:%.*]], label [[BB6]]
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15 | 15 | ; CHECK: for.preheader:
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16 | 16 | ; CHECK-NEXT: [[T1_0_LCSSA:%.*]] = phi i8* [ [[T1_0]], [[BB6]] ]
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17 |
| -; CHECK-NEXT: [[T1_0_LCSSA1:%.*]] = ptrtoint i8* [[T1_0_LCSSA]] to i64 |
18 |
| -; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 [[T1_0_LCSSA1]] to i32 |
19 |
| -; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[ARR2]] to i32 |
20 |
| -; CHECK-NEXT: [[TMP2:%.*]] = sub i32 [[TMP0]], [[TMP1]] |
21 |
| -; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP2]], 4 |
| 17 | +; CHECK-NEXT: [[T1_0_LCSSA2:%.*]] = ptrtoint i8* [[T1_0_LCSSA]] to i64 |
| 18 | +; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 [[ARR1]] to i32 |
| 19 | +; CHECK-NEXT: [[TMP1:%.*]] = sub i32 0, [[TMP0]] |
| 20 | +; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[T1_0_LCSSA2]] to i32 |
| 21 | +; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[TMP1]], [[TMP2]] |
| 22 | +; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP3]], 4 |
22 | 23 | ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]]
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23 | 24 | ; CHECK: vector.scevcheck:
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24 |
| -; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[T1_0_LCSSA1]], -1 |
25 |
| -; CHECK-NEXT: [[TMP4:%.*]] = sub i64 [[TMP3]], [[ARR2]] |
26 |
| -; CHECK-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i8 |
27 |
| -; CHECK-NEXT: [[MUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 1, i8 [[TMP5]]) |
| 25 | +; CHECK-NEXT: [[TMP4:%.*]] = sub i64 -1, [[ARR1]] |
| 26 | +; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[TMP4]], [[T1_0_LCSSA2]] |
| 27 | +; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i8 |
| 28 | +; CHECK-NEXT: [[MUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 1, i8 [[TMP6]]) |
28 | 29 | ; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i8, i1 } [[MUL]], 0
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29 | 30 | ; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i8, i1 } [[MUL]], 1
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30 |
| -; CHECK-NEXT: [[TMP6:%.*]] = add i8 1, [[MUL_RESULT]] |
31 |
| -; CHECK-NEXT: [[TMP7:%.*]] = sub i8 1, [[MUL_RESULT]] |
32 |
| -; CHECK-NEXT: [[TMP8:%.*]] = icmp sgt i8 [[TMP7]], 1 |
33 |
| -; CHECK-NEXT: [[TMP9:%.*]] = icmp slt i8 [[TMP6]], 1 |
34 |
| -; CHECK-NEXT: [[TMP10:%.*]] = select i1 false, i1 [[TMP8]], i1 [[TMP9]] |
35 |
| -; CHECK-NEXT: [[TMP11:%.*]] = icmp ugt i64 [[TMP4]], 255 |
36 |
| -; CHECK-NEXT: [[TMP12:%.*]] = or i1 [[TMP10]], [[TMP11]] |
37 |
| -; CHECK-NEXT: [[TMP13:%.*]] = or i1 [[TMP12]], [[MUL_OVERFLOW]] |
38 |
| -; CHECK-NEXT: [[TMP14:%.*]] = or i1 false, [[TMP13]] |
39 |
| -; CHECK-NEXT: br i1 [[TMP14]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] |
| 31 | +; CHECK-NEXT: [[TMP7:%.*]] = add i8 1, [[MUL_RESULT]] |
| 32 | +; CHECK-NEXT: [[TMP8:%.*]] = sub i8 1, [[MUL_RESULT]] |
| 33 | +; CHECK-NEXT: [[TMP9:%.*]] = icmp sgt i8 [[TMP8]], 1 |
| 34 | +; CHECK-NEXT: [[TMP10:%.*]] = icmp slt i8 [[TMP7]], 1 |
| 35 | +; CHECK-NEXT: [[TMP11:%.*]] = select i1 false, i1 [[TMP9]], i1 [[TMP10]] |
| 36 | +; CHECK-NEXT: [[TMP12:%.*]] = icmp ugt i64 [[TMP5]], 255 |
| 37 | +; CHECK-NEXT: [[TMP13:%.*]] = or i1 [[TMP11]], [[TMP12]] |
| 38 | +; CHECK-NEXT: [[TMP14:%.*]] = or i1 [[TMP13]], [[MUL_OVERFLOW]] |
| 39 | +; CHECK-NEXT: [[TMP15:%.*]] = or i1 false, [[TMP14]] |
| 40 | +; CHECK-NEXT: br i1 [[TMP15]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] |
40 | 41 | ; CHECK: vector.ph:
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41 |
| -; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP2]], 4 |
42 |
| -; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP2]], [[N_MOD_VF]] |
| 42 | +; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP3]], 4 |
| 43 | +; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP3]], [[N_MOD_VF]] |
43 | 44 | ; CHECK-NEXT: [[IND_END:%.*]] = trunc i32 [[N_VEC]] to i8
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44 | 45 | ; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i8> poison, i8 [[T9:%.*]], i32 0
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45 | 46 | ; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i8> [[BROADCAST_SPLATINSERT]], <4 x i8> poison, <4 x i32> zeroinitializer
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46 | 47 | ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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47 | 48 | ; CHECK: vector.body:
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48 | 49 | ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
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49 | 50 | ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i8> [ <i8 0, i8 1, i8 2, i8 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
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50 |
| -; CHECK-NEXT: [[TMP15:%.*]] = add <4 x i8> [[VEC_IND]], <i8 1, i8 1, i8 1, i8 1> |
51 |
| -; CHECK-NEXT: [[TMP16:%.*]] = extractelement <4 x i8> [[TMP15]], i32 0 |
52 |
| -; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i8, i8* [[ARR]], i8 [[TMP16]] |
53 |
| -; CHECK-NEXT: [[TMP18:%.*]] = icmp slt <4 x i8> [[TMP15]], [[BROADCAST_SPLAT]] |
54 |
| -; CHECK-NEXT: [[TMP19:%.*]] = zext <4 x i1> [[TMP18]] to <4 x i8> |
55 |
| -; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds i8, i8* [[TMP17]], i32 0 |
56 |
| -; CHECK-NEXT: [[TMP21:%.*]] = bitcast i8* [[TMP20]] to <4 x i8>* |
57 |
| -; CHECK-NEXT: store <4 x i8> [[TMP19]], <4 x i8>* [[TMP21]], align 1 |
| 51 | +; CHECK-NEXT: [[TMP16:%.*]] = add <4 x i8> [[VEC_IND]], <i8 1, i8 1, i8 1, i8 1> |
| 52 | +; CHECK-NEXT: [[TMP17:%.*]] = extractelement <4 x i8> [[TMP16]], i32 0 |
| 53 | +; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i8, i8* [[ARR]], i8 [[TMP17]] |
| 54 | +; CHECK-NEXT: [[TMP19:%.*]] = icmp slt <4 x i8> [[TMP16]], [[BROADCAST_SPLAT]] |
| 55 | +; CHECK-NEXT: [[TMP20:%.*]] = zext <4 x i1> [[TMP19]] to <4 x i8> |
| 56 | +; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i8, i8* [[TMP18]], i32 0 |
| 57 | +; CHECK-NEXT: [[TMP22:%.*]] = bitcast i8* [[TMP21]] to <4 x i8>* |
| 58 | +; CHECK-NEXT: store <4 x i8> [[TMP20]], <4 x i8>* [[TMP22]], align 1 |
58 | 59 | ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
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59 | 60 | ; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i8> [[VEC_IND]], <i8 4, i8 4, i8 4, i8 4>
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60 |
| -; CHECK-NEXT: [[TMP22:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] |
61 |
| -; CHECK-NEXT: br i1 [[TMP22]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] |
| 61 | +; CHECK-NEXT: [[TMP23:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] |
| 62 | +; CHECK-NEXT: br i1 [[TMP23]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] |
62 | 63 | ; CHECK: middle.block:
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63 |
| -; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP2]], [[N_VEC]] |
| 64 | +; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP3]], [[N_VEC]] |
64 | 65 | ; CHECK-NEXT: br i1 [[CMP_N]], label [[FOR_EXIT:%.*]], label [[SCALAR_PH]]
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65 | 66 | ; CHECK: scalar.ph:
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66 | 67 | ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i8 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0, [[FOR_PREHEADER]] ], [ 0, [[VECTOR_SCEVCHECK]] ]
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