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[X86] Remove patterns for shift/rotate with immediate 1 and optimize during MC lowering
It's first suggested by @craig.topper in D150068. I think there are at least three pros 1. This can reduce the patterns during ISEL, as a result, reducing the bytes in X86GenDAGISel.inc 2. The patterns for shift/rotate with immediate 1 look quite similar to shift/rotate with immediate 8. So this can be seen as eliminating "duplicate" code. 3. Delay the optimization from imm8 to imm1, so that the previous optimization passes do not need to handle the version of imm1 It improves fast isel code and makes X86DomainReassignment work for shifts by 1, but regressed global isel, though no one should care. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D150107
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+73
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11 files changed

+73
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‎llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -37705,10 +37705,11 @@ X86TargetLowering::emitLongJmpShadowStackFix(MachineInstr &MI,
3770537705
fixShadowMBB->addSuccessor(fixShadowLoopPrepareMBB);
3770637706

3770737707
// Do a single shift left.
37708-
unsigned ShlR1Opc = (PVT == MVT::i64) ? X86::SHL64r1 : X86::SHL32r1;
37708+
unsigned ShlR1Opc = (PVT == MVT::i64) ? X86::SHL64ri : X86::SHL32ri;
3770937709
Register SspAfterShlReg = MRI.createVirtualRegister(PtrRC);
3771037710
BuildMI(fixShadowLoopPrepareMBB, DL, TII->get(ShlR1Opc), SspAfterShlReg)
37711-
.addReg(SspSecondShrReg);
37711+
.addReg(SspSecondShrReg)
37712+
.addImm(1);
3771237713

3771337714
// Save the value 128 to a register (will be used next with incssp).
3771437715
Register Value128InReg = MRI.createVirtualRegister(PtrRC);

‎llvm/lib/Target/X86/X86InstrInfo.cpp

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4256,9 +4256,6 @@ inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag,
42564256
case X86::SBB16rr: case X86::SBB8rr: case X86::SBB64rm:
42574257
case X86::SBB32rm: case X86::SBB16rm: case X86::SBB8rm:
42584258
case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
4259-
case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
4260-
case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
4261-
case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
42624259
case X86::LZCNT16rr: case X86::LZCNT16rm:
42634260
case X86::LZCNT32rr: case X86::LZCNT32rm:
42644261
case X86::LZCNT64rr: case X86::LZCNT64rm:

‎llvm/lib/Target/X86/X86InstrShiftRotate.td

Lines changed: 48 additions & 104 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212

1313
// FIXME: Someone needs to smear multipattern goodness all over this file.
1414

15-
let Defs = [EFLAGS] in {
15+
let Defs = [EFLAGS], hasSideEffects = 0 in {
1616

1717
let Constraints = "$src1 = $dst" in {
1818
let Uses = [CL], SchedRW = [WriteShiftCL] in {
@@ -50,9 +50,6 @@ def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
5050
[(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
5151
} // isConvertibleToThreeAddress = 1
5252

53-
// NOTE: We don't include patterns for shifts of a register by one, because
54-
// 'add reg,reg' is cheaper (and we have a Pat pattern for shift-by-one).
55-
let hasSideEffects = 0 in {
5653
def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
5754
"shl{b}\t$dst", []>;
5855
def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
@@ -61,7 +58,6 @@ def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
6158
"shl{l}\t$dst", []>, OpSize32;
6259
def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
6360
"shl{q}\t$dst", []>;
64-
} // hasSideEffects = 0
6561
} // SchedRW
6662
} // Constraints = "$src = $dst"
6763

@@ -85,7 +81,7 @@ def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
8581
Requires<[In64BitMode]>;
8682
} // Uses, SchedRW
8783

88-
let SchedRW = [WriteShiftLd, WriteRMW] in {
84+
let SchedRW = [WriteShiftLd, WriteRMW], mayLoad = 1, mayStore = 1 in {
8985
def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, u8imm:$src),
9086
"shl{b}\t{$src, $dst|$dst, $src}",
9187
[(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
@@ -104,21 +100,14 @@ def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, u8imm:$src),
104100

105101
// Shift by 1
106102
def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
107-
"shl{b}\t$dst",
108-
[(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
103+
"shl{b}\t$dst", []>;
109104
def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
110-
"shl{w}\t$dst",
111-
[(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
112-
OpSize16;
105+
"shl{w}\t$dst", []>, OpSize16;
113106
def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
114-
"shl{l}\t$dst",
115-
[(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>,
116-
OpSize32;
107+
"shl{l}\t$dst", []>, OpSize32;
117108
def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
118-
"shl{q}\t$dst",
119-
[(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>,
120-
Requires<[In64BitMode]>;
121-
} // SchedRW
109+
"shl{q}\t$dst", []>, Requires<[In64BitMode]>;
110+
} // SchedRW, mayLoad, mayStore
122111

123112
let Constraints = "$src1 = $dst" in {
124113
let Uses = [CL], SchedRW = [WriteShiftCL] in {
@@ -154,17 +143,13 @@ def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$src2),
154143

155144
// Shift right by 1
156145
def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
157-
"shr{b}\t$dst",
158-
[(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
146+
"shr{b}\t$dst", []>;
159147
def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
160-
"shr{w}\t$dst",
161-
[(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize16;
148+
"shr{w}\t$dst", []>, OpSize16;
162149
def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
163-
"shr{l}\t$dst",
164-
[(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>, OpSize32;
150+
"shr{l}\t$dst", []>, OpSize32;
165151
def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
166-
"shr{q}\t$dst",
167-
[(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
152+
"shr{q}\t$dst", []>;
168153
} // SchedRW
169154
} // Constraints = "$src = $dst"
170155

@@ -187,7 +172,7 @@ def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
187172
Requires<[In64BitMode]>;
188173
} // Uses, SchedRW
189174

190-
let SchedRW = [WriteShiftLd, WriteRMW] in {
175+
let SchedRW = [WriteShiftLd, WriteRMW], mayLoad = 1, mayStore = 1 in {
191176
def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, u8imm:$src),
192177
"shr{b}\t{$src, $dst|$dst, $src}",
193178
[(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
@@ -206,21 +191,15 @@ def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, u8imm:$src),
206191

207192
// Shift by 1
208193
def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
209-
"shr{b}\t$dst",
210-
[(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
194+
"shr{b}\t$dst", []>;
211195
def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
212-
"shr{w}\t$dst",
213-
[(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
214-
OpSize16;
196+
"shr{w}\t$dst", []>, OpSize16;
215197
def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
216-
"shr{l}\t$dst",
217-
[(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>,
218-
OpSize32;
198+
"shr{l}\t$dst", []>, OpSize32;
219199
def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
220-
"shr{q}\t$dst",
221-
[(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>,
222-
Requires<[In64BitMode]>;
223-
} // SchedRW
200+
"shr{q}\t$dst", []>, Requires<[In64BitMode]>;
201+
} // SchedRW, mayLoad, mayStore
202+
224203

225204
let Constraints = "$src1 = $dst" in {
226205
let Uses = [CL], SchedRW = [WriteShiftCL] in {
@@ -259,17 +238,13 @@ def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
259238

260239
// Shift by 1
261240
def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
262-
"sar{b}\t$dst",
263-
[(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
241+
"sar{b}\t$dst", []>;
264242
def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
265-
"sar{w}\t$dst",
266-
[(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize16;
243+
"sar{w}\t$dst", []>, OpSize16;
267244
def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
268-
"sar{l}\t$dst",
269-
[(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>, OpSize32;
245+
"sar{l}\t$dst", []>, OpSize32;
270246
def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
271-
"sar{q}\t$dst",
272-
[(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
247+
"sar{q}\t$dst", []>;
273248
} // SchedRW
274249
} // Constraints = "$src = $dst"
275250

@@ -292,7 +267,7 @@ def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
292267
Requires<[In64BitMode]>;
293268
} // Uses, SchedRW
294269

295-
let SchedRW = [WriteShiftLd, WriteRMW] in {
270+
let SchedRW = [WriteShiftLd, WriteRMW], mayLoad = 1, mayStore = 1 in {
296271
def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, u8imm:$src),
297272
"sar{b}\t{$src, $dst|$dst, $src}",
298273
[(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
@@ -311,27 +286,19 @@ def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, u8imm:$src),
311286

312287
// Shift by 1
313288
def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
314-
"sar{b}\t$dst",
315-
[(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
289+
"sar{b}\t$dst", []>;
316290
def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
317-
"sar{w}\t$dst",
318-
[(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
319-
OpSize16;
291+
"sar{w}\t$dst", []>, OpSize16;
320292
def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
321-
"sar{l}\t$dst",
322-
[(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>,
323-
OpSize32;
293+
"sar{l}\t$dst", []>, OpSize32;
324294
def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
325-
"sar{q}\t$dst",
326-
[(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>,
327-
Requires<[In64BitMode]>;
295+
"sar{q}\t$dst", []>, Requires<[In64BitMode]>;
328296
} // SchedRW
329297

330298
//===----------------------------------------------------------------------===//
331299
// Rotate instructions
332300
//===----------------------------------------------------------------------===//
333301

334-
let hasSideEffects = 0 in {
335302
let Constraints = "$src1 = $dst" in {
336303

337304
let Uses = [CL, EFLAGS], SchedRW = [WriteRotateCL] in {
@@ -393,7 +360,6 @@ def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
393360
def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$cnt),
394361
"rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
395362
} // Uses = [EFLAGS], SchedRW
396-
397363
} // Constraints = "$src = $dst"
398364

399365
let mayLoad = 1, mayStore = 1 in {
@@ -457,7 +423,6 @@ def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
457423
Requires<[In64BitMode]>;
458424
} // Uses = [CL, EFLAGS], SchedRW
459425
} // mayLoad, mayStore
460-
} // hasSideEffects = 0
461426

462427
let Constraints = "$src1 = $dst" in {
463428
// FIXME: provide shorter instructions when imm8 == 1
@@ -495,17 +460,13 @@ def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
495460

496461
// Rotate by 1
497462
def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
498-
"rol{b}\t$dst",
499-
[(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
463+
"rol{b}\t$dst", []>;
500464
def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
501-
"rol{w}\t$dst",
502-
[(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize16;
465+
"rol{w}\t$dst", []>, OpSize16;
503466
def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
504-
"rol{l}\t$dst",
505-
[(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>, OpSize32;
467+
"rol{l}\t$dst", []>, OpSize32;
506468
def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
507-
"rol{q}\t$dst",
508-
[(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
469+
"rol{q}\t$dst", []>;
509470
} // SchedRW
510471
} // Constraints = "$src = $dst"
511472

@@ -525,7 +486,7 @@ def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
525486
Requires<[In64BitMode]>;
526487
} // Uses, SchedRW
527488

528-
let SchedRW = [WriteRotateLd, WriteRMW] in {
489+
let SchedRW = [WriteRotateLd, WriteRMW], mayLoad = 1, mayStore = 1 in {
529490
def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, u8imm:$src1),
530491
"rol{b}\t{$src1, $dst|$dst, $src1}",
531492
[(store (rotl (loadi8 addr:$dst), (i8 imm:$src1)), addr:$dst)]>;
@@ -544,21 +505,14 @@ def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, u8imm:$src1),
544505

545506
// Rotate by 1
546507
def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
547-
"rol{b}\t$dst",
548-
[(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
508+
"rol{b}\t$dst", []>;
549509
def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
550-
"rol{w}\t$dst",
551-
[(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
552-
OpSize16;
510+
"rol{w}\t$dst", []>, OpSize16;
553511
def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
554-
"rol{l}\t$dst",
555-
[(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>,
556-
OpSize32;
512+
"rol{l}\t$dst", []>, OpSize32;
557513
def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
558-
"rol{q}\t$dst",
559-
[(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>,
560-
Requires<[In64BitMode]>;
561-
} // SchedRW
514+
"rol{q}\t$dst", []>, Requires<[In64BitMode]>;
515+
} // SchedRW, mayLoad, mayStore
562516

563517
let Constraints = "$src1 = $dst" in {
564518
let Uses = [CL], SchedRW = [WriteRotateCL] in {
@@ -595,17 +549,13 @@ def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
595549

596550
// Rotate by 1
597551
def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
598-
"ror{b}\t$dst",
599-
[(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
552+
"ror{b}\t$dst", []>;
600553
def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
601-
"ror{w}\t$dst",
602-
[(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize16;
554+
"ror{w}\t$dst", []>, OpSize16;
603555
def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
604-
"ror{l}\t$dst",
605-
[(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>, OpSize32;
556+
"ror{l}\t$dst", []>, OpSize32;
606557
def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
607-
"ror{q}\t$dst",
608-
[(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
558+
"ror{q}\t$dst", []>;
609559
} // SchedRW
610560
} // Constraints = "$src = $dst", SchedRW
611561

@@ -625,7 +575,7 @@ def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
625575
Requires<[In64BitMode]>;
626576
} // Uses, SchedRW
627577

628-
let SchedRW = [WriteRotateLd, WriteRMW] in {
578+
let SchedRW = [WriteRotateLd, WriteRMW], mayLoad = 1, mayStore =1 in {
629579
def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, u8imm:$src),
630580
"ror{b}\t{$src, $dst|$dst, $src}",
631581
[(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
@@ -644,21 +594,15 @@ def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, u8imm:$src),
644594

645595
// Rotate by 1
646596
def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
647-
"ror{b}\t$dst",
648-
[(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
597+
"ror{b}\t$dst", []>;
649598
def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
650-
"ror{w}\t$dst",
651-
[(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
652-
OpSize16;
599+
"ror{w}\t$dst", []>, OpSize16;
653600
def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
654-
"ror{l}\t$dst",
655-
[(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>,
601+
"ror{l}\t$dst", []>,
656602
OpSize32;
657603
def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
658-
"ror{q}\t$dst",
659-
[(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>,
660-
Requires<[In64BitMode]>;
661-
} // SchedRW
604+
"ror{q}\t$dst", []>, Requires<[In64BitMode]>;
605+
} // SchedRW, mayLoad, mayStore
662606

663607

664608
//===----------------------------------------------------------------------===//
@@ -816,7 +760,7 @@ def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
816760
TB;
817761
} // SchedRW
818762

819-
} // Defs = [EFLAGS]
763+
} // Defs = [EFLAGS], hasSideEffects
820764

821765
// Use the opposite rotate if allows us to use the rotate by 1 instruction.
822766
def : Pat<(rotl GR8:$src1, (i8 7)), (ROR8r1 GR8:$src1)>;

‎llvm/lib/Target/X86/X86MCInstLower.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -505,6 +505,9 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
505505
if (X86::optimizeInstFromVEX3ToVEX2(OutMI, MI->getDesc()))
506506
return;
507507

508+
if (X86::optimizeShiftRotateWithImmediateOne(OutMI))
509+
return;
510+
508511
// Handle a few special cases to eliminate operand modifiers.
509512
switch (OutMI.getOpcode()) {
510513
case X86::LEA64_32r:

‎llvm/test/CodeGen/X86/GlobalISel/ashr-scalar.ll

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -167,7 +167,8 @@ define i1 @test_ashr_i1_imm1(i32 %arg1) {
167167
; X64-NEXT: movl %edi, %eax
168168
; X64-NEXT: shlb $7, %al
169169
; X64-NEXT: sarb $7, %al
170-
; X64-NEXT: sarb %al
170+
; X64-NEXT: movb $1, %cl
171+
; X64-NEXT: sarb %cl, %al
171172
; X64-NEXT: # kill: def $al killed $al killed $eax
172173
; X64-NEXT: retq
173174
%a = trunc i32 %arg1 to i1

‎llvm/test/CodeGen/X86/GlobalISel/lshr-scalar.ll

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -165,7 +165,8 @@ define i1 @test_lshr_i1_imm1(i32 %arg1) {
165165
; X64: # %bb.0:
166166
; X64-NEXT: movl %edi, %eax
167167
; X64-NEXT: andb $1, %al
168-
; X64-NEXT: shrb %al
168+
; X64-NEXT: movb $1, %cl
169+
; X64-NEXT: shrb %cl, %al
169170
; X64-NEXT: # kill: def $al killed $al killed $eax
170171
; X64-NEXT: retq
171172
%a = trunc i32 %arg1 to i1

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