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[RISCV] Fix crash in lowerVECTOR_DEINTERLEAVE when VecVT is an LMUL=8 type.
If VecVT is an LMUL=8 VT, we can't concatenate the vectors as that would create an illegal type. Instead we need to split the vectors and emit two VECTOR_DEINTERLEAVE operations that can each be lowered. Reviewed By: luke, rogfer01 Differential Revision: https://reviews.llvm.org/D152402
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‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7633,6 +7633,25 @@ SDValue RISCVTargetLowering::lowerVECTOR_DEINTERLEAVE(SDValue Op,
76337633
if (VecVT.getVectorElementType() == MVT::i1)
76347634
return widenVectorOpsToi8(Op, DL, DAG);
76357635

7636+
// If the VT is LMUL=8, we need to split and reassemble.
7637+
if (VecVT.getSizeInBits().getKnownMinValue() ==
7638+
(8 * RISCV::RVVBitsPerBlock)) {
7639+
auto [Op0Lo, Op0Hi] = DAG.SplitVectorOperand(Op.getNode(), 0);
7640+
auto [Op1Lo, Op1Hi] = DAG.SplitVectorOperand(Op.getNode(), 1);
7641+
EVT SplitVT = Op0Lo.getValueType();
7642+
7643+
SDValue ResLo = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL,
7644+
DAG.getVTList(SplitVT, SplitVT), Op0Lo, Op0Hi);
7645+
SDValue ResHi = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL,
7646+
DAG.getVTList(SplitVT, SplitVT), Op1Lo, Op1Hi);
7647+
7648+
SDValue Even = DAG.getNode(ISD::CONCAT_VECTORS, DL, VecVT,
7649+
ResLo.getValue(0), ResHi.getValue(0));
7650+
SDValue Odd = DAG.getNode(ISD::CONCAT_VECTORS, DL, VecVT, ResLo.getValue(1),
7651+
ResHi.getValue(1));
7652+
return DAG.getMergeValues({Even, Odd}, DL);
7653+
}
7654+
76367655
// Concatenate the two vectors as one vector to deinterleave
76377656
MVT ConcatVT =
76387657
MVT::getVectorVT(VecVT.getVectorElementType(),

‎llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll

Lines changed: 291 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh | FileCheck %s
3-
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh | FileCheck %s
2+
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+zfh,+experimental-zvfh | FileCheck %s
3+
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zfh,+experimental-zvfh | FileCheck %s
44

55
; Integers
66

@@ -88,6 +88,172 @@ declare {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.experimental.vector.deint
8888
declare {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.experimental.vector.deinterleave2.nxv8i32(<vscale x 8 x i32>)
8989
declare {<vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.experimental.vector.deinterleave2.nxv4i64(<vscale x 4 x i64>)
9090

91+
define {<vscale x 64 x i1>, <vscale x 64 x i1>} @vector_deinterleave_nxv64i1_nxv128i1(<vscale x 128 x i1> %vec) {
92+
; CHECK-LABEL: vector_deinterleave_nxv64i1_nxv128i1:
93+
; CHECK: # %bb.0:
94+
; CHECK-NEXT: vmv1r.v v28, v8
95+
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
96+
; CHECK-NEXT: vmv.v.i v8, 0
97+
; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
98+
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
99+
; CHECK-NEXT: vnsrl.wi v24, v16, 0
100+
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
101+
; CHECK-NEXT: vmv1r.v v0, v28
102+
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
103+
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
104+
; CHECK-NEXT: vnsrl.wi v28, v8, 0
105+
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
106+
; CHECK-NEXT: vmsne.vi v0, v24, 0
107+
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
108+
; CHECK-NEXT: vnsrl.wi v24, v16, 8
109+
; CHECK-NEXT: vnsrl.wi v28, v8, 8
110+
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
111+
; CHECK-NEXT: vmsne.vi v8, v24, 0
112+
; CHECK-NEXT: ret
113+
%retval = call {<vscale x 64 x i1>, <vscale x 64 x i1>} @llvm.experimental.vector.deinterleave2.nxv128i1(<vscale x 128 x i1> %vec)
114+
ret {<vscale x 64 x i1>, <vscale x 64 x i1>} %retval
115+
}
116+
117+
define {<vscale x 64 x i8>, <vscale x 64 x i8>} @vector_deinterleave_nxv64i8_nxv128i8(<vscale x 128 x i8> %vec) {
118+
; CHECK-LABEL: vector_deinterleave_nxv64i8_nxv128i8:
119+
; CHECK: # %bb.0:
120+
; CHECK-NEXT: vmv8r.v v24, v8
121+
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
122+
; CHECK-NEXT: vnsrl.wi v8, v24, 0
123+
; CHECK-NEXT: vnsrl.wi v12, v16, 0
124+
; CHECK-NEXT: vnsrl.wi v0, v24, 8
125+
; CHECK-NEXT: vnsrl.wi v4, v16, 8
126+
; CHECK-NEXT: vmv8r.v v16, v0
127+
; CHECK-NEXT: ret
128+
%retval = call {<vscale x 64 x i8>, <vscale x 64 x i8>} @llvm.experimental.vector.deinterleave2.nxv128i8(<vscale x 128 x i8> %vec)
129+
ret {<vscale x 64 x i8>, <vscale x 64 x i8>} %retval
130+
}
131+
132+
define {<vscale x 32 x i16>, <vscale x 32 x i16>} @vector_deinterleave_nxv32i16_nxv64i16(<vscale x 64 x i16> %vec) {
133+
; CHECK-LABEL: vector_deinterleave_nxv32i16_nxv64i16:
134+
; CHECK: # %bb.0:
135+
; CHECK-NEXT: vmv8r.v v24, v8
136+
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
137+
; CHECK-NEXT: vnsrl.wi v8, v24, 0
138+
; CHECK-NEXT: vnsrl.wi v12, v16, 0
139+
; CHECK-NEXT: vnsrl.wi v0, v24, 16
140+
; CHECK-NEXT: vnsrl.wi v4, v16, 16
141+
; CHECK-NEXT: vmv8r.v v16, v0
142+
; CHECK-NEXT: ret
143+
%retval = call {<vscale x 32 x i16>, <vscale x 32 x i16>} @llvm.experimental.vector.deinterleave2.nxv64i16(<vscale x 64 x i16> %vec)
144+
ret {<vscale x 32 x i16>, <vscale x 32 x i16>} %retval
145+
}
146+
147+
define {<vscale x 16 x i32>, <vscale x 16 x i32>} @vector_deinterleave_nxv16i32_nxvv32i32(<vscale x 32 x i32> %vec) {
148+
; CHECK-LABEL: vector_deinterleave_nxv16i32_nxvv32i32:
149+
; CHECK: # %bb.0:
150+
; CHECK-NEXT: vmv8r.v v24, v16
151+
; CHECK-NEXT: li a0, 32
152+
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
153+
; CHECK-NEXT: vnsrl.wx v20, v24, a0
154+
; CHECK-NEXT: vnsrl.wx v16, v8, a0
155+
; CHECK-NEXT: vnsrl.wi v0, v8, 0
156+
; CHECK-NEXT: vnsrl.wi v4, v24, 0
157+
; CHECK-NEXT: vmv8r.v v8, v0
158+
; CHECK-NEXT: ret
159+
%retval = call {<vscale x 16 x i32>, <vscale x 16 x i32>} @llvm.experimental.vector.deinterleave2.nxv32i32(<vscale x 32 x i32> %vec)
160+
ret {<vscale x 16 x i32>, <vscale x 16 x i32>} %retval
161+
}
162+
163+
define {<vscale x 8 x i64>, <vscale x 8 x i64>} @vector_deinterleave_nxv8i64_nxv16i64(<vscale x 16 x i64> %vec) {
164+
; CHECK-LABEL: vector_deinterleave_nxv8i64_nxv16i64:
165+
; CHECK: # %bb.0:
166+
; CHECK-NEXT: addi sp, sp, -16
167+
; CHECK-NEXT: .cfi_def_cfa_offset 16
168+
; CHECK-NEXT: csrr a0, vlenb
169+
; CHECK-NEXT: li a1, 40
170+
; CHECK-NEXT: mul a0, a0, a1
171+
; CHECK-NEXT: sub sp, sp, a0
172+
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb
173+
; CHECK-NEXT: csrr a0, vlenb
174+
; CHECK-NEXT: li a1, 24
175+
; CHECK-NEXT: mul a0, a0, a1
176+
; CHECK-NEXT: add a0, sp, a0
177+
; CHECK-NEXT: addi a0, a0, 16
178+
; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
179+
; CHECK-NEXT: vmv8r.v v24, v8
180+
; CHECK-NEXT: csrr a0, vlenb
181+
; CHECK-NEXT: slli a0, a0, 4
182+
; CHECK-NEXT: add a0, sp, a0
183+
; CHECK-NEXT: addi a0, a0, 16
184+
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
185+
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
186+
; CHECK-NEXT: vid.v v8
187+
; CHECK-NEXT: vadd.vv v0, v8, v8
188+
; CHECK-NEXT: vrgather.vv v8, v24, v0
189+
; CHECK-NEXT: vrgather.vv v24, v16, v0
190+
; CHECK-NEXT: csrr a0, vlenb
191+
; CHECK-NEXT: slli a0, a0, 5
192+
; CHECK-NEXT: add a0, sp, a0
193+
; CHECK-NEXT: addi a0, a0, 16
194+
; CHECK-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
195+
; CHECK-NEXT: vadd.vi v16, v0, 1
196+
; CHECK-NEXT: csrr a0, vlenb
197+
; CHECK-NEXT: slli a0, a0, 3
198+
; CHECK-NEXT: add a0, sp, a0
199+
; CHECK-NEXT: addi a0, a0, 16
200+
; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
201+
; CHECK-NEXT: csrr a0, vlenb
202+
; CHECK-NEXT: slli a0, a0, 4
203+
; CHECK-NEXT: add a0, sp, a0
204+
; CHECK-NEXT: addi a0, a0, 16
205+
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
206+
; CHECK-NEXT: vrgather.vv v0, v24, v16
207+
; CHECK-NEXT: addi a0, sp, 16
208+
; CHECK-NEXT: vs8r.v v0, (a0) # Unknown-size Folded Spill
209+
; CHECK-NEXT: csrr a0, vlenb
210+
; CHECK-NEXT: li a1, 24
211+
; CHECK-NEXT: mul a0, a0, a1
212+
; CHECK-NEXT: add a0, sp, a0
213+
; CHECK-NEXT: addi a0, a0, 16
214+
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
215+
; CHECK-NEXT: csrr a0, vlenb
216+
; CHECK-NEXT: slli a0, a0, 3
217+
; CHECK-NEXT: add a0, sp, a0
218+
; CHECK-NEXT: addi a0, a0, 16
219+
; CHECK-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload
220+
; CHECK-NEXT: vrgather.vv v16, v24, v0
221+
; CHECK-NEXT: csrr a0, vlenb
222+
; CHECK-NEXT: slli a0, a0, 4
223+
; CHECK-NEXT: add a0, sp, a0
224+
; CHECK-NEXT: addi a0, a0, 16
225+
; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
226+
; CHECK-NEXT: csrr a0, vlenb
227+
; CHECK-NEXT: slli a0, a0, 5
228+
; CHECK-NEXT: add a0, sp, a0
229+
; CHECK-NEXT: addi a0, a0, 16
230+
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
231+
; CHECK-NEXT: vmv4r.v v12, v16
232+
; CHECK-NEXT: csrr a0, vlenb
233+
; CHECK-NEXT: slli a0, a0, 4
234+
; CHECK-NEXT: add a0, sp, a0
235+
; CHECK-NEXT: addi a0, a0, 16
236+
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
237+
; CHECK-NEXT: addi a0, sp, 16
238+
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
239+
; CHECK-NEXT: vmv4r.v v28, v16
240+
; CHECK-NEXT: vmv8r.v v16, v24
241+
; CHECK-NEXT: csrr a0, vlenb
242+
; CHECK-NEXT: li a1, 40
243+
; CHECK-NEXT: mul a0, a0, a1
244+
; CHECK-NEXT: add sp, sp, a0
245+
; CHECK-NEXT: addi sp, sp, 16
246+
; CHECK-NEXT: ret
247+
%retval = call {<vscale x 8 x i64>, <vscale x 8 x i64>} @llvm.experimental.vector.deinterleave2.nxv16i64(<vscale x 16 x i64> %vec)
248+
ret {<vscale x 8 x i64>, <vscale x 8 x i64>} %retval
249+
}
250+
251+
declare {<vscale x 64 x i1>, <vscale x 64 x i1>} @llvm.experimental.vector.deinterleave2.nxv128i1(<vscale x 128 x i1>)
252+
declare {<vscale x 64 x i8>, <vscale x 64 x i8>} @llvm.experimental.vector.deinterleave2.nxv128i8(<vscale x 128 x i8>)
253+
declare {<vscale x 32 x i16>, <vscale x 32 x i16>} @llvm.experimental.vector.deinterleave2.nxv64i16(<vscale x 64 x i16>)
254+
declare {<vscale x 16 x i32>, <vscale x 16 x i32>} @llvm.experimental.vector.deinterleave2.nxv32i32(<vscale x 32 x i32>)
255+
declare {<vscale x 8 x i64>, <vscale x 8 x i64>} @llvm.experimental.vector.deinterleave2.nxv16i64(<vscale x 16 x i64>)
256+
91257
; Floats
92258

93259
define {<vscale x 2 x half>, <vscale x 2 x half>} @vector_deinterleave_nxv2f16_nxv4f16(<vscale x 4 x half> %vec) {
@@ -178,3 +344,126 @@ declare {<vscale x 2 x float>, <vscale x 2 x float>} @llvm.experimental.vector.d
178344
declare {<vscale x 8 x half>, <vscale x 8 x half>} @llvm.experimental.vector.deinterleave2.nxv16f16(<vscale x 16 x half>)
179345
declare {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.experimental.vector.deinterleave2.nxv8f32(<vscale x 8 x float>)
180346
declare {<vscale x 2 x double>, <vscale x 2 x double>} @llvm.experimental.vector.deinterleave2.nxv4f64(<vscale x 4 x double>)
347+
348+
define {<vscale x 32 x half>, <vscale x 32 x half>} @vector_deinterleave_nxv32f16_nxv64f16(<vscale x 64 x half> %vec) {
349+
; CHECK-LABEL: vector_deinterleave_nxv32f16_nxv64f16:
350+
; CHECK: # %bb.0:
351+
; CHECK-NEXT: vmv8r.v v24, v8
352+
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
353+
; CHECK-NEXT: vnsrl.wi v8, v24, 0
354+
; CHECK-NEXT: vnsrl.wi v12, v16, 0
355+
; CHECK-NEXT: vnsrl.wi v0, v24, 16
356+
; CHECK-NEXT: vnsrl.wi v4, v16, 16
357+
; CHECK-NEXT: vmv8r.v v16, v0
358+
; CHECK-NEXT: ret
359+
%retval = call {<vscale x 32 x half>, <vscale x 32 x half>} @llvm.experimental.vector.deinterleave2.nxv64f16(<vscale x 64 x half> %vec)
360+
ret {<vscale x 32 x half>, <vscale x 32 x half>} %retval
361+
}
362+
363+
define {<vscale x 16 x float>, <vscale x 16 x float>} @vector_deinterleave_nxv16f32_nxv32f32(<vscale x 32 x float> %vec) {
364+
; CHECK-LABEL: vector_deinterleave_nxv16f32_nxv32f32:
365+
; CHECK: # %bb.0:
366+
; CHECK-NEXT: vmv8r.v v24, v16
367+
; CHECK-NEXT: li a0, 32
368+
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
369+
; CHECK-NEXT: vnsrl.wx v20, v24, a0
370+
; CHECK-NEXT: vnsrl.wx v16, v8, a0
371+
; CHECK-NEXT: vnsrl.wi v0, v8, 0
372+
; CHECK-NEXT: vnsrl.wi v4, v24, 0
373+
; CHECK-NEXT: vmv8r.v v8, v0
374+
; CHECK-NEXT: ret
375+
%retval = call {<vscale x 16 x float>, <vscale x 16 x float>} @llvm.experimental.vector.deinterleave2.nxv32f32(<vscale x 32 x float> %vec)
376+
ret {<vscale x 16 x float>, <vscale x 16 x float>} %retval
377+
}
378+
379+
define {<vscale x 8 x double>, <vscale x 8 x double>} @vector_deinterleave_nxv8f64_nxv16f64(<vscale x 16 x double> %vec) {
380+
; CHECK-LABEL: vector_deinterleave_nxv8f64_nxv16f64:
381+
; CHECK: # %bb.0:
382+
; CHECK-NEXT: addi sp, sp, -16
383+
; CHECK-NEXT: .cfi_def_cfa_offset 16
384+
; CHECK-NEXT: csrr a0, vlenb
385+
; CHECK-NEXT: li a1, 40
386+
; CHECK-NEXT: mul a0, a0, a1
387+
; CHECK-NEXT: sub sp, sp, a0
388+
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb
389+
; CHECK-NEXT: csrr a0, vlenb
390+
; CHECK-NEXT: li a1, 24
391+
; CHECK-NEXT: mul a0, a0, a1
392+
; CHECK-NEXT: add a0, sp, a0
393+
; CHECK-NEXT: addi a0, a0, 16
394+
; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
395+
; CHECK-NEXT: vmv8r.v v24, v8
396+
; CHECK-NEXT: csrr a0, vlenb
397+
; CHECK-NEXT: slli a0, a0, 4
398+
; CHECK-NEXT: add a0, sp, a0
399+
; CHECK-NEXT: addi a0, a0, 16
400+
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
401+
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
402+
; CHECK-NEXT: vid.v v8
403+
; CHECK-NEXT: vadd.vv v0, v8, v8
404+
; CHECK-NEXT: vrgather.vv v8, v24, v0
405+
; CHECK-NEXT: vrgather.vv v24, v16, v0
406+
; CHECK-NEXT: csrr a0, vlenb
407+
; CHECK-NEXT: slli a0, a0, 5
408+
; CHECK-NEXT: add a0, sp, a0
409+
; CHECK-NEXT: addi a0, a0, 16
410+
; CHECK-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
411+
; CHECK-NEXT: vadd.vi v16, v0, 1
412+
; CHECK-NEXT: csrr a0, vlenb
413+
; CHECK-NEXT: slli a0, a0, 3
414+
; CHECK-NEXT: add a0, sp, a0
415+
; CHECK-NEXT: addi a0, a0, 16
416+
; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
417+
; CHECK-NEXT: csrr a0, vlenb
418+
; CHECK-NEXT: slli a0, a0, 4
419+
; CHECK-NEXT: add a0, sp, a0
420+
; CHECK-NEXT: addi a0, a0, 16
421+
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
422+
; CHECK-NEXT: vrgather.vv v0, v24, v16
423+
; CHECK-NEXT: addi a0, sp, 16
424+
; CHECK-NEXT: vs8r.v v0, (a0) # Unknown-size Folded Spill
425+
; CHECK-NEXT: csrr a0, vlenb
426+
; CHECK-NEXT: li a1, 24
427+
; CHECK-NEXT: mul a0, a0, a1
428+
; CHECK-NEXT: add a0, sp, a0
429+
; CHECK-NEXT: addi a0, a0, 16
430+
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
431+
; CHECK-NEXT: csrr a0, vlenb
432+
; CHECK-NEXT: slli a0, a0, 3
433+
; CHECK-NEXT: add a0, sp, a0
434+
; CHECK-NEXT: addi a0, a0, 16
435+
; CHECK-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload
436+
; CHECK-NEXT: vrgather.vv v16, v24, v0
437+
; CHECK-NEXT: csrr a0, vlenb
438+
; CHECK-NEXT: slli a0, a0, 4
439+
; CHECK-NEXT: add a0, sp, a0
440+
; CHECK-NEXT: addi a0, a0, 16
441+
; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
442+
; CHECK-NEXT: csrr a0, vlenb
443+
; CHECK-NEXT: slli a0, a0, 5
444+
; CHECK-NEXT: add a0, sp, a0
445+
; CHECK-NEXT: addi a0, a0, 16
446+
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
447+
; CHECK-NEXT: vmv4r.v v12, v16
448+
; CHECK-NEXT: csrr a0, vlenb
449+
; CHECK-NEXT: slli a0, a0, 4
450+
; CHECK-NEXT: add a0, sp, a0
451+
; CHECK-NEXT: addi a0, a0, 16
452+
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
453+
; CHECK-NEXT: addi a0, sp, 16
454+
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
455+
; CHECK-NEXT: vmv4r.v v28, v16
456+
; CHECK-NEXT: vmv8r.v v16, v24
457+
; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: li a1, 40
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; CHECK-NEXT: mul a0, a0, a1
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; CHECK-NEXT: add sp, sp, a0
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: ret
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%retval = call {<vscale x 8 x double>, <vscale x 8 x double>} @llvm.experimental.vector.deinterleave2.nxv16f64(<vscale x 16 x double> %vec)
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ret {<vscale x 8 x double>, <vscale x 8 x double>} %retval
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}
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declare {<vscale x 32 x half>, <vscale x 32 x half>} @llvm.experimental.vector.deinterleave2.nxv64f16(<vscale x 64 x half>)
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declare {<vscale x 16 x float>, <vscale x 16 x float>} @llvm.experimental.vector.deinterleave2.nxv32f32(<vscale x 32 x float>)
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declare {<vscale x 8 x double>, <vscale x 8 x double>} @llvm.experimental.vector.deinterleave2.nxv16f64(<vscale x 16 x double>)

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