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[GlobalISel] Check if ShiftAmt is greater then size of operand
matchCombineShlOfExtend did not check if the size of new shift would be wider then a size of operand. Current condition did not work if the value being shifted was zero. Updated to support vector splat. Patch by: Acim Maravic Differential Revision: https://reviews.llvm.org/D151122
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5 files changed

+320
-160
lines changed

5 files changed

+320
-160
lines changed

‎llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1722,9 +1722,9 @@ bool CombinerHelper::matchCombineShlOfExtend(MachineInstr &MI,
17221722
!mi_match(LHS, MRI, m_GSExt(m_Reg(ExtSrc))))
17231723
return false;
17241724

1725-
// TODO: Should handle vector splat.
17261725
Register RHS = MI.getOperand(2).getReg();
1727-
auto MaybeShiftAmtVal = getIConstantVRegValWithLookThrough(RHS, MRI);
1726+
MachineInstr *MIShiftAmt = MRI.getVRegDef(RHS);
1727+
auto MaybeShiftAmtVal = isConstantOrConstantSplatVector(*MIShiftAmt, MRI);
17281728
if (!MaybeShiftAmtVal)
17291729
return false;
17301730

@@ -1739,12 +1739,13 @@ bool CombinerHelper::matchCombineShlOfExtend(MachineInstr &MI,
17391739
return false;
17401740
}
17411741

1742-
int64_t ShiftAmt = MaybeShiftAmtVal->Value.getSExtValue();
1742+
int64_t ShiftAmt = MaybeShiftAmtVal->getSExtValue();
17431743
MatchData.Reg = ExtSrc;
17441744
MatchData.Imm = ShiftAmt;
17451745

17461746
unsigned MinLeadingZeros = KB->getKnownZeroes(ExtSrc).countl_one();
1747-
return MinLeadingZeros >= ShiftAmt;
1747+
unsigned SrcTySize = MRI.getType(ExtSrc).getScalarSizeInBits();
1748+
return MinLeadingZeros >= ShiftAmt && ShiftAmt < SrcTySize;
17481749
}
17491750

17501751
void CombinerHelper::applyCombineShlOfExtend(MachineInstr &MI,

‎llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-divrem-insertpt-crash.mir

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -17,18 +17,20 @@ body: |
1717
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
1818
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF
1919
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
20+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
2021
; CHECK-NEXT: G_BRCOND [[DEF]](s1), %bb.2
2122
; CHECK-NEXT: G_BR %bb.1
2223
; CHECK-NEXT: {{ $}}
2324
; CHECK-NEXT: bb.1:
2425
; CHECK-NEXT: successors: %bb.2(0x80000000)
2526
; CHECK-NEXT: {{ $}}
26-
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
27-
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C1]](s32)
28-
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
29-
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s64) = G_FREEZE [[C2]]
27+
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
28+
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C2]](s32)
29+
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
30+
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s64) = G_FREEZE [[C3]]
3031
; CHECK-NEXT: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[FREEZE]], [[C]]
31-
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ZEXT]], [[UDIV]]
32+
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C1]](s64)
33+
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[SHL]], [[UDIV]]
3234
; CHECK-NEXT: G_STORE [[ADD]](s64), [[COPY]](p0) :: (store (s64))
3335
; CHECK-NEXT: {{ $}}
3436
; CHECK-NEXT: bb.2:

‎llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.postlegal.mir

Lines changed: 102 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -327,3 +327,105 @@ body: |
327327
%shl:_(s64) = G_SHL %extend, %shiftamt
328328
$vgpr0_vgpr1 = COPY %shl
329329
...
330+
331+
---
332+
name: do_not_shl_s32_zero_by_16_from_zext_s16
333+
tracksRegLiveness: true
334+
legalized: true
335+
336+
body: |
337+
bb.0:
338+
liveins: $vgpr0
339+
; GFX6-LABEL: name: do_not_shl_s32_zero_by_16_from_zext_s16
340+
; GFX6: liveins: $vgpr0
341+
; GFX6-NEXT: {{ $}}
342+
; GFX6-NEXT: %zero:_(s16) = G_CONSTANT i16 0
343+
; GFX6-NEXT: %extend:_(s32) = G_ZEXT %zero(s16)
344+
; GFX6-NEXT: %shiftamt:_(s16) = G_CONSTANT i16 16
345+
; GFX6-NEXT: %shl:_(s32) = G_SHL %extend, %shiftamt(s16)
346+
; GFX6-NEXT: $vgpr0 = COPY %shl(s32)
347+
; GFX9-LABEL: name: do_not_shl_s32_zero_by_16_from_zext_s16
348+
; GFX9: liveins: $vgpr0
349+
; GFX9-NEXT: {{ $}}
350+
; GFX9-NEXT: %zero:_(s16) = G_CONSTANT i16 0
351+
; GFX9-NEXT: %extend:_(s32) = G_ZEXT %zero(s16)
352+
; GFX9-NEXT: %shiftamt:_(s16) = G_CONSTANT i16 16
353+
; GFX9-NEXT: %shl:_(s32) = G_SHL %extend, %shiftamt(s16)
354+
; GFX9-NEXT: $vgpr0 = COPY %shl(s32)
355+
%zero:_(s16) = G_CONSTANT i16 0
356+
%extend:_(s32) = G_ZEXT %zero:_(s16)
357+
%shiftamt:_(s16) = G_CONSTANT i16 16
358+
%shl:_(s32) = G_SHL %extend, %shiftamt(s16)
359+
$vgpr0 = COPY %shl
360+
...
361+
362+
---
363+
name: do_not_shl_v2s32_zero_by_16_from_zext_v2s16
364+
tracksRegLiveness: true
365+
legalized: true
366+
367+
body: |
368+
bb.0:
369+
liveins: $vgpr0
370+
; GFX6-LABEL: name: do_not_shl_v2s32_zero_by_16_from_zext_v2s16
371+
; GFX6: liveins: $vgpr0
372+
; GFX6-NEXT: {{ $}}
373+
; GFX6-NEXT: %zero:_(s16) = G_CONSTANT i16 0
374+
; GFX6-NEXT: %zerovector:_(<2 x s16>) = G_BUILD_VECTOR %zero(s16), %zero(s16)
375+
; GFX6-NEXT: %shiftamt:_(s16) = G_CONSTANT i16 16
376+
; GFX6-NEXT: %shiftamtvector:_(<2 x s16>) = G_BUILD_VECTOR %shiftamt(s16), %shiftamt(s16)
377+
; GFX6-NEXT: %extend:_(<2 x s32>) = G_ZEXT %zerovector(<2 x s16>)
378+
; GFX6-NEXT: %shl:_(<2 x s32>) = G_SHL %extend, %shiftamtvector(<2 x s16>)
379+
; GFX6-NEXT: $vgpr0_vgpr1 = COPY %shl(<2 x s32>)
380+
; GFX9-LABEL: name: do_not_shl_v2s32_zero_by_16_from_zext_v2s16
381+
; GFX9: liveins: $vgpr0
382+
; GFX9-NEXT: {{ $}}
383+
; GFX9-NEXT: %zero:_(s16) = G_CONSTANT i16 0
384+
; GFX9-NEXT: %zerovector:_(<2 x s16>) = G_BUILD_VECTOR %zero(s16), %zero(s16)
385+
; GFX9-NEXT: %shiftamt:_(s16) = G_CONSTANT i16 16
386+
; GFX9-NEXT: %shiftamtvector:_(<2 x s16>) = G_BUILD_VECTOR %shiftamt(s16), %shiftamt(s16)
387+
; GFX9-NEXT: %extend:_(<2 x s32>) = G_ZEXT %zerovector(<2 x s16>)
388+
; GFX9-NEXT: %shl:_(<2 x s32>) = G_SHL %extend, %shiftamtvector(<2 x s16>)
389+
; GFX9-NEXT: $vgpr0_vgpr1 = COPY %shl(<2 x s32>)
390+
%zero:_(s16) = G_CONSTANT i16 0
391+
%zerovector:_(<2 x s16>) = G_BUILD_VECTOR %zero, %zero:_(s16)
392+
%shiftamt:_(s16) = G_CONSTANT i16 16
393+
%shiftamtvector:_(<2 x s16>) = G_BUILD_VECTOR %shiftamt, %shiftamt:_(s16)
394+
%extend:_(<2 x s32>) = G_ZEXT %zerovector:_(<2 x s16>)
395+
%shl:_(<2 x s32>) = G_SHL %extend, %shiftamtvector
396+
$vgpr0_vgpr1 = COPY %shl
397+
...
398+
399+
---
400+
name: do_not_shl_s32_by_16_from_zext_s16
401+
tracksRegLiveness: true
402+
legalized: true
403+
404+
body: |
405+
bb.0:
406+
liveins: $vgpr0
407+
; GFX6-LABEL: name: do_not_shl_s32_by_16_from_zext_s16
408+
; GFX6: liveins: $vgpr0
409+
; GFX6-NEXT: {{ $}}
410+
; GFX6-NEXT: %argument:_(s32) = COPY $vgpr0
411+
; GFX6-NEXT: %truncate:_(s16) = G_TRUNC %argument(s32)
412+
; GFX6-NEXT: %shiftamt:_(s16) = G_CONSTANT i16 16
413+
; GFX6-NEXT: %extend:_(s32) = G_ZEXT %truncate(s16)
414+
; GFX6-NEXT: %shl:_(s32) = G_SHL %extend, %shiftamt(s16)
415+
; GFX6-NEXT: $vgpr0 = COPY %shl(s32)
416+
; GFX9-LABEL: name: do_not_shl_s32_by_16_from_zext_s16
417+
; GFX9: liveins: $vgpr0
418+
; GFX9-NEXT: {{ $}}
419+
; GFX9-NEXT: %argument:_(s32) = COPY $vgpr0
420+
; GFX9-NEXT: %truncate:_(s16) = G_TRUNC %argument(s32)
421+
; GFX9-NEXT: %shiftamt:_(s16) = G_CONSTANT i16 16
422+
; GFX9-NEXT: %extend:_(s32) = G_ZEXT %truncate(s16)
423+
; GFX9-NEXT: %shl:_(s32) = G_SHL %extend, %shiftamt(s16)
424+
; GFX9-NEXT: $vgpr0 = COPY %shl(s32)
425+
%argument:_(s32) = COPY $vgpr0
426+
%truncate:_(s16) = G_TRUNC %argument:_(s32)
427+
%shiftamt:_(s16) = G_CONSTANT i16 16
428+
%extend:_(s32) = G_ZEXT %truncate:_(s16)
429+
%shl:_(s32) = G_SHL %extend, %shiftamt(s16)
430+
$vgpr0 = COPY %shl
431+
...

‎llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.prelegal.mir

Lines changed: 114 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -134,10 +134,10 @@ body: |
134134
; GFX6-NEXT: %masklow14:_(s16) = G_CONSTANT i16 16383
135135
; GFX6-NEXT: %masklow14vec:_(<2 x s16>) = G_BUILD_VECTOR %masklow14(s16), %masklow14(s16)
136136
; GFX6-NEXT: %masked:_(<2 x s16>) = G_AND %narrow, %masklow14vec
137-
; GFX6-NEXT: %extend:_(<2 x s32>) = G_ZEXT %masked(<2 x s16>)
138-
; GFX6-NEXT: %shiftamt:_(s32) = G_CONSTANT i32 2
139-
; GFX6-NEXT: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
140-
; GFX6-NEXT: %shl:_(<2 x s32>) = G_SHL %extend, %shiftamtvec(<2 x s32>)
137+
; GFX6-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
138+
; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)
139+
; GFX6-NEXT: [[SHL:%[0-9]+]]:_(<2 x s16>) = G_SHL %masked, [[BUILD_VECTOR]](<2 x s16>)
140+
; GFX6-NEXT: %shl:_(<2 x s32>) = G_ZEXT [[SHL]](<2 x s16>)
141141
; GFX6-NEXT: $vgpr0_vgpr1 = COPY %shl(<2 x s32>)
142142
; GFX9-LABEL: name: narrow_shl_v2s32_by_2_from_zext_v2s16
143143
; GFX9: liveins: $vgpr0
@@ -146,10 +146,10 @@ body: |
146146
; GFX9-NEXT: %masklow14:_(s16) = G_CONSTANT i16 16383
147147
; GFX9-NEXT: %masklow14vec:_(<2 x s16>) = G_BUILD_VECTOR %masklow14(s16), %masklow14(s16)
148148
; GFX9-NEXT: %masked:_(<2 x s16>) = G_AND %narrow, %masklow14vec
149-
; GFX9-NEXT: %extend:_(<2 x s32>) = G_ZEXT %masked(<2 x s16>)
150-
; GFX9-NEXT: %shiftamt:_(s32) = G_CONSTANT i32 2
151-
; GFX9-NEXT: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
152-
; GFX9-NEXT: %shl:_(<2 x s32>) = G_SHL %extend, %shiftamtvec(<2 x s32>)
149+
; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
150+
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)
151+
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(<2 x s16>) = G_SHL %masked, [[BUILD_VECTOR]](<2 x s16>)
152+
; GFX9-NEXT: %shl:_(<2 x s32>) = G_ZEXT [[SHL]](<2 x s16>)
153153
; GFX9-NEXT: $vgpr0_vgpr1 = COPY %shl(<2 x s32>)
154154
%narrow:_(<2 x s16>) = COPY $vgpr0
155155
%masklow14:_(s16) = G_CONSTANT i16 16383
@@ -176,10 +176,10 @@ body: |
176176
; GFX6-NEXT: %masklow30:_(s32) = G_CONSTANT i32 1073741823
177177
; GFX6-NEXT: %masklow30vec:_(<2 x s32>) = G_BUILD_VECTOR %masklow30(s32), %masklow30(s32)
178178
; GFX6-NEXT: %masked:_(<2 x s32>) = G_AND %narrow, %masklow30vec
179-
; GFX6-NEXT: %extend:_(<2 x s64>) = G_ANYEXT %masked(<2 x s32>)
180179
; GFX6-NEXT: %shiftamt:_(s32) = G_CONSTANT i32 2
181180
; GFX6-NEXT: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
182-
; GFX6-NEXT: %shl:_(<2 x s64>) = G_SHL %extend, %shiftamtvec(<2 x s32>)
181+
; GFX6-NEXT: [[SHL:%[0-9]+]]:_(<2 x s32>) = G_SHL %masked, %shiftamtvec(<2 x s32>)
182+
; GFX6-NEXT: %shl:_(<2 x s64>) = G_ZEXT [[SHL]](<2 x s32>)
183183
; GFX6-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %shl(<2 x s64>)
184184
; GFX9-LABEL: name: narrow_shl_v2s64_by_2_from_anyext_v2s32
185185
; GFX9: liveins: $vgpr0_vgpr1
@@ -188,10 +188,10 @@ body: |
188188
; GFX9-NEXT: %masklow30:_(s32) = G_CONSTANT i32 1073741823
189189
; GFX9-NEXT: %masklow30vec:_(<2 x s32>) = G_BUILD_VECTOR %masklow30(s32), %masklow30(s32)
190190
; GFX9-NEXT: %masked:_(<2 x s32>) = G_AND %narrow, %masklow30vec
191-
; GFX9-NEXT: %extend:_(<2 x s64>) = G_ANYEXT %masked(<2 x s32>)
192191
; GFX9-NEXT: %shiftamt:_(s32) = G_CONSTANT i32 2
193192
; GFX9-NEXT: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
194-
; GFX9-NEXT: %shl:_(<2 x s64>) = G_SHL %extend, %shiftamtvec(<2 x s32>)
193+
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(<2 x s32>) = G_SHL %masked, %shiftamtvec(<2 x s32>)
194+
; GFX9-NEXT: %shl:_(<2 x s64>) = G_ZEXT [[SHL]](<2 x s32>)
195195
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %shl(<2 x s64>)
196196
%narrow:_(<2 x s32>) = COPY $vgpr0_vgpr1
197197
%masklow30:_(s32) = G_CONSTANT i32 1073741823
@@ -203,3 +203,105 @@ body: |
203203
%shl:_(<2 x s64>) = G_SHL %extend, %shiftamtvec
204204
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %shl
205205
...
206+
207+
---
208+
name: do_not_shl_s32_zero_by_16_from_zext_s16
209+
tracksRegLiveness: true
210+
legalized: true
211+
212+
body: |
213+
bb.0:
214+
liveins: $vgpr0
215+
; GFX6-LABEL: name: do_not_shl_s32_zero_by_16_from_zext_s16
216+
; GFX6: liveins: $vgpr0
217+
; GFX6-NEXT: {{ $}}
218+
; GFX6-NEXT: %zero:_(s16) = G_CONSTANT i16 0
219+
; GFX6-NEXT: %extend:_(s32) = G_ZEXT %zero(s16)
220+
; GFX6-NEXT: %shiftamt:_(s16) = G_CONSTANT i16 16
221+
; GFX6-NEXT: %shl:_(s32) = G_SHL %extend, %shiftamt(s16)
222+
; GFX6-NEXT: $vgpr0 = COPY %shl(s32)
223+
; GFX9-LABEL: name: do_not_shl_s32_zero_by_16_from_zext_s16
224+
; GFX9: liveins: $vgpr0
225+
; GFX9-NEXT: {{ $}}
226+
; GFX9-NEXT: %zero:_(s16) = G_CONSTANT i16 0
227+
; GFX9-NEXT: %extend:_(s32) = G_ZEXT %zero(s16)
228+
; GFX9-NEXT: %shiftamt:_(s16) = G_CONSTANT i16 16
229+
; GFX9-NEXT: %shl:_(s32) = G_SHL %extend, %shiftamt(s16)
230+
; GFX9-NEXT: $vgpr0 = COPY %shl(s32)
231+
%zero:_(s16) = G_CONSTANT i16 0
232+
%extend:_(s32) = G_ZEXT %zero:_(s16)
233+
%shiftamt:_(s16) = G_CONSTANT i16 16
234+
%shl:_(s32) = G_SHL %extend, %shiftamt(s16)
235+
$vgpr0 = COPY %shl
236+
...
237+
238+
---
239+
name: do_not_shl_v2s32_zero_by_16_from_zext_v2s16
240+
tracksRegLiveness: true
241+
legalized: true
242+
243+
body: |
244+
bb.0:
245+
liveins: $vgpr0, $vgpr1
246+
; GFX6-LABEL: name: do_not_shl_v2s32_zero_by_16_from_zext_v2s16
247+
; GFX6: liveins: $vgpr0, $vgpr1
248+
; GFX6-NEXT: {{ $}}
249+
; GFX6-NEXT: %zero:_(s16) = G_CONSTANT i16 0
250+
; GFX6-NEXT: %zerovector:_(<2 x s16>) = G_BUILD_VECTOR %zero(s16), %zero(s16)
251+
; GFX6-NEXT: %shiftamt:_(s16) = G_CONSTANT i16 16
252+
; GFX6-NEXT: %shiftamtvector:_(<2 x s16>) = G_BUILD_VECTOR %shiftamt(s16), %shiftamt(s16)
253+
; GFX6-NEXT: %extend:_(<2 x s32>) = G_ZEXT %zerovector(<2 x s16>)
254+
; GFX6-NEXT: %shl:_(<2 x s32>) = G_SHL %extend, %shiftamtvector(<2 x s16>)
255+
; GFX6-NEXT: $vgpr0_vgpr1 = COPY %shl(<2 x s32>)
256+
; GFX9-LABEL: name: do_not_shl_v2s32_zero_by_16_from_zext_v2s16
257+
; GFX9: liveins: $vgpr0, $vgpr1
258+
; GFX9-NEXT: {{ $}}
259+
; GFX9-NEXT: %zero:_(s16) = G_CONSTANT i16 0
260+
; GFX9-NEXT: %zerovector:_(<2 x s16>) = G_BUILD_VECTOR %zero(s16), %zero(s16)
261+
; GFX9-NEXT: %shiftamt:_(s16) = G_CONSTANT i16 16
262+
; GFX9-NEXT: %shiftamtvector:_(<2 x s16>) = G_BUILD_VECTOR %shiftamt(s16), %shiftamt(s16)
263+
; GFX9-NEXT: %extend:_(<2 x s32>) = G_ZEXT %zerovector(<2 x s16>)
264+
; GFX9-NEXT: %shl:_(<2 x s32>) = G_SHL %extend, %shiftamtvector(<2 x s16>)
265+
; GFX9-NEXT: $vgpr0_vgpr1 = COPY %shl(<2 x s32>)
266+
%zero:_(s16) = G_CONSTANT i16 0
267+
%zerovector:_(<2 x s16>) = G_BUILD_VECTOR %zero, %zero:_(s16)
268+
%shiftamt:_(s16) = G_CONSTANT i16 16
269+
%shiftamtvector:_(<2 x s16>) = G_BUILD_VECTOR %shiftamt, %shiftamt:_(s16)
270+
%extend:_(<2 x s32>) = G_ZEXT %zerovector:_(<2 x s16>)
271+
%shl:_(<2 x s32>) = G_SHL %extend, %shiftamtvector
272+
$vgpr0_vgpr1 = COPY %shl
273+
...
274+
275+
---
276+
name: do_not_shl_s32_by_16_from_zext_s16
277+
tracksRegLiveness: true
278+
legalized: true
279+
280+
body: |
281+
bb.0:
282+
liveins: $vgpr0
283+
; GFX6-LABEL: name: do_not_shl_s32_by_16_from_zext_s16
284+
; GFX6: liveins: $vgpr0
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; GFX6-NEXT: {{ $}}
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; GFX6-NEXT: %argument:_(s32) = COPY $vgpr0
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; GFX6-NEXT: %truncate:_(s16) = G_TRUNC %argument(s32)
288+
; GFX6-NEXT: %shiftamt:_(s16) = G_CONSTANT i16 16
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; GFX6-NEXT: %extend:_(s32) = G_ZEXT %truncate(s16)
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; GFX6-NEXT: %shl:_(s32) = G_SHL %extend, %shiftamt(s16)
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; GFX6-NEXT: $vgpr0 = COPY %shl(s32)
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; GFX9-LABEL: name: do_not_shl_s32_by_16_from_zext_s16
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; GFX9: liveins: $vgpr0
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; GFX9-NEXT: {{ $}}
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; GFX9-NEXT: %argument:_(s32) = COPY $vgpr0
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; GFX9-NEXT: %truncate:_(s16) = G_TRUNC %argument(s32)
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; GFX9-NEXT: %shiftamt:_(s16) = G_CONSTANT i16 16
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; GFX9-NEXT: %extend:_(s32) = G_ZEXT %truncate(s16)
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; GFX9-NEXT: %shl:_(s32) = G_SHL %extend, %shiftamt(s16)
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; GFX9-NEXT: $vgpr0 = COPY %shl(s32)
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%argument:_(s32) = COPY $vgpr0
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%truncate:_(s16) = G_TRUNC %argument:_(s32)
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%shiftamt:_(s16) = G_CONSTANT i16 16
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%extend:_(s32) = G_ZEXT %truncate:_(s16)
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%shl:_(s32) = G_SHL %extend, %shiftamt(s16)
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$vgpr0 = COPY %shl
307+
...

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