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Tim Renouf
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[AMDGPU] Added target-specific attribute amdgpu-max-memory-clause
With LLPC, previous investigation has suggested that si-scheduler interacts badly with SiFormMemoryClauses on an XNACK target in some games. That needs further investigation in the future. In the meantime, this commit adds a target-specific attribute to allow us to disable SIFormMemoryClauses by setting it to 1 on a per-function basis for LLPC to use. Differential Revision: https://reviews.llvm.org/D62572 Change-Id: Ia0ca12ce79093cbbe86caded723ffb13384ede92 llvm-svn: 362127
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‎llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp

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@@ -319,6 +319,8 @@ bool SIFormMemoryClauses::runOnMachineFunction(MachineFunction &MF) {
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MaxVGPRs = TRI->getAllocatableSet(MF, &AMDGPU::VGPR_32RegClass).count();
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MaxSGPRs = TRI->getAllocatableSet(MF, &AMDGPU::SGPR_32RegClass).count();
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unsigned FuncMaxClause = AMDGPU::getIntegerAttribute(
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MF.getFunction(), "amdgpu-max-memory-clause", MaxClause);
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for (MachineBasicBlock &MBB : MF) {
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MachineBasicBlock::instr_iterator Next;
@@ -339,7 +341,7 @@ bool SIFormMemoryClauses::runOnMachineFunction(MachineFunction &MF) {
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continue;
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unsigned Length = 1;
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for ( ; Next != E && Length < MaxClause; ++Next) {
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for ( ; Next != E && Length < FuncMaxClause; ++Next) {
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if (!isValidClauseInst(*Next, IsVMEM))
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break;
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‎llvm/test/CodeGen/AMDGPU/disable_form_clauses.ll

Lines changed: 65 additions & 0 deletions
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@@ -0,0 +1,65 @@
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; RUN: llc -march=amdgcn -mcpu=gfx902 -verify-machineinstrs -amdgpu-enable-global-sgpr-addr -stop-after=si-form-memory-clauses < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}name:{{[ ]*}}vector_clause
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; GCN: BUNDLE
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; GCN-NEXT: LOAD_DWORDX2
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; GCN-NEXT: LOAD_DWORDX2
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; GCN-NEXT: {{^ *[}]}}
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define amdgpu_kernel void @vector_clause(<4 x i32> addrspace(1)* noalias nocapture readonly %arg, <4 x i32> addrspace(1)* noalias nocapture %arg1) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp2 = zext i32 %tmp to i64
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%tmp3 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp2
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%tmp4 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp3, align 16
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%tmp5 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp2
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%tmp6 = add nuw nsw i64 %tmp2, 1
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%tmp7 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp6
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%tmp8 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp7, align 16
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%tmp9 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp6
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%tmp10 = add nuw nsw i64 %tmp2, 2
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%tmp11 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp10
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%tmp12 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp11, align 16
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%tmp13 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp10
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%tmp14 = add nuw nsw i64 %tmp2, 3
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%tmp15 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp14
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%tmp16 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp15, align 16
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%tmp17 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp14
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store <4 x i32> %tmp4, <4 x i32> addrspace(1)* %tmp5, align 16
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store <4 x i32> %tmp8, <4 x i32> addrspace(1)* %tmp9, align 16
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store <4 x i32> %tmp12, <4 x i32> addrspace(1)* %tmp13, align 16
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store <4 x i32> %tmp16, <4 x i32> addrspace(1)* %tmp17, align 16
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ret void
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}
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; GCN-LABEL: {{^}}name:{{[ ]*}}no_vector_clause
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; GCN-NOT: BUNDLE
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define amdgpu_kernel void @no_vector_clause(<4 x i32> addrspace(1)* noalias nocapture readonly %arg, <4 x i32> addrspace(1)* noalias nocapture %arg1) #0 {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp2 = zext i32 %tmp to i64
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%tmp3 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp2
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%tmp4 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp3, align 16
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%tmp5 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp2
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%tmp6 = add nuw nsw i64 %tmp2, 1
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%tmp7 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp6
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%tmp8 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp7, align 16
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%tmp9 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp6
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%tmp10 = add nuw nsw i64 %tmp2, 2
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%tmp11 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp10
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%tmp12 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp11, align 16
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%tmp13 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp10
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%tmp14 = add nuw nsw i64 %tmp2, 3
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%tmp15 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp14
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%tmp16 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp15, align 16
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%tmp17 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp14
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store <4 x i32> %tmp4, <4 x i32> addrspace(1)* %tmp5, align 16
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store <4 x i32> %tmp8, <4 x i32> addrspace(1)* %tmp9, align 16
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store <4 x i32> %tmp12, <4 x i32> addrspace(1)* %tmp13, align 16
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store <4 x i32> %tmp16, <4 x i32> addrspace(1)* %tmp17, align 16
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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attributes #0 = { "amdgpu-max-memory-clause"="1" }
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