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Krzysztof Parzyszek
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[Hexagon] Add more patterns for HVX loads and stores
In particular, add patterns for loads/stores to the stack (with a frame index as address).
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2 files changed

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‎llvm/lib/Target/Hexagon/HexagonPatternsHVX.td

Lines changed: 69 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -95,21 +95,41 @@ def unalignedstore: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{
9595

9696
// HVX loads
9797

98-
multiclass HvxLd_pat<InstHexagon MI, PatFrag Load, ValueType ResType,
98+
multiclass HvxLdfi_pat<InstHexagon MI, PatFrag Load, ValueType ResType,
99+
PatFrag ImmPred> {
100+
def: Pat<(ResType (Load (add (i32 AddrFI:$fi), ImmPred:$Off))),
101+
(MI AddrFI:$fi, imm:$Off)>;
102+
def: Pat<(ResType (Load (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off))),
103+
(MI AddrFI:$fi, imm:$Off)>;
104+
def: Pat<(ResType (Load AddrFI:$fi)), (ResType (MI AddrFI:$fi, 0))>;
105+
}
106+
107+
multiclass HvxLdgi_pat<InstHexagon MI, PatFrag Load, ValueType ResType,
99108
PatFrag ImmPred> {
109+
def: Pat<(ResType (Load (add I32:$Rt, ImmPred:$Off))),
110+
(MI I32:$Rt, imm:$Off)>;
100111
def: Pat<(ResType (Load I32:$Rt)),
101112
(MI I32:$Rt, 0)>;
102-
def: Pat<(ResType (Load (add I32:$Rt, ImmPred:$s))),
103-
(MI I32:$Rt, imm:$s)>;
113+
}
114+
115+
multiclass HvxLdc_pat<InstHexagon MI, PatFrag Load, ValueType ResType> {
104116
// The HVX selection code for shuffles can generate vector constants.
105117
// Calling "Select" on the resulting loads from CP fails without these
106118
// patterns.
107-
def: Pat<(ResType (Load (HexagonCP tconstpool:$A))),
108-
(MI (A2_tfrsi imm:$A), 0)>;
109-
def: Pat<(ResType (Load (HexagonAtPcrel tconstpool:$A))),
110-
(MI (C4_addipc imm:$A), 0)>;
119+
def: Pat<(ResType (Load (HexagonCP tconstpool:$Addr))),
120+
(MI (A2_tfrsi imm:$Addr), 0)>;
121+
def: Pat<(ResType (Load (HexagonAtPcrel tconstpool:$Addr))),
122+
(MI (C4_addipc imm:$Addr), 0)>;
123+
}
124+
125+
multiclass HvxLd_pat<InstHexagon MI, PatFrag Load, ValueType ResType,
126+
PatFrag ImmPred> {
127+
defm: HvxLdfi_pat<MI, Load, ResType, ImmPred>;
128+
defm: HvxLdgi_pat<MI, Load, ResType, ImmPred>;
129+
defm: HvxLdc_pat <MI, Load, ResType>;
111130
}
112131

132+
// Aligned loads: everything, plus loads with valignaddr node.
113133
multiclass HvxLda_pat<InstHexagon MI, PatFrag Load, ValueType ResType,
114134
PatFrag ImmPred> {
115135
let AddedComplexity = 50 in {
@@ -122,41 +142,61 @@ multiclass HvxLda_pat<InstHexagon MI, PatFrag Load, ValueType ResType,
122142
}
123143

124144
let Predicates = [UseHVX] in {
145+
// alignedload will match a non-temporal load as well, so try non-temporal
146+
// first.
125147
defm: HvxLda_pat<V6_vL32b_nt_ai, alignednontemporalload, VecI8, IsVecOff>;
126148
defm: HvxLda_pat<V6_vL32b_nt_ai, alignednontemporalload, VecI16, IsVecOff>;
127149
defm: HvxLda_pat<V6_vL32b_nt_ai, alignednontemporalload, VecI32, IsVecOff>;
150+
defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI8, IsVecOff>;
151+
defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI16, IsVecOff>;
152+
defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI32, IsVecOff>;
128153

129-
defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI8, IsVecOff>;
130-
defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI16, IsVecOff>;
131-
defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI32, IsVecOff>;
132-
133-
defm: HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecI8, IsVecOff>;
134-
defm: HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecI16, IsVecOff>;
135-
defm: HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecI32, IsVecOff>;
154+
defm: HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecI8, IsVecOff>;
155+
defm: HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecI16, IsVecOff>;
156+
defm: HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecI32, IsVecOff>;
136157
}
137158

159+
138160
// HVX stores
139161

140-
multiclass HvxSt_pat<InstHexagon MI, PatFrag Store, PatFrag ImmPred,
141-
PatFrag Value> {
162+
multiclass HvxStfi_pat<InstHexagon MI, PatFrag Store, PatFrag Value,
163+
PatFrag ImmPred> {
164+
def: Pat<(Store Value:$Vs, (add (i32 AddrFI:$fi), ImmPred:$Off)),
165+
(MI AddrFI:$fi, imm:$Off, Value:$Vs)>;
166+
def: Pat<(Store Value:$Vs, (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off)),
167+
(MI AddrFI:$fi, imm:$Off, Value:$Vs)>;
168+
def: Pat<(Store Value:$Vs, AddrFI:$fi),
169+
(MI AddrFI:$fi, 0, Value:$Vs)>;
170+
}
171+
172+
multiclass HvxStgi_pat<InstHexagon MI, PatFrag Store, PatFrag Value,
173+
PatFrag ImmPred> {
174+
def: Pat<(Store Value:$Vs, (add I32:$Rt, ImmPred:$Off)),
175+
(MI I32:$Rt, imm:$Off, Value:$Vs)>;
176+
def: Pat<(Store Value:$Vs, (IsOrAdd I32:$Rt, ImmPred:$Off)),
177+
(MI I32:$Rt, imm:$Off, Value:$Vs)>;
142178
def: Pat<(Store Value:$Vs, I32:$Rt),
143179
(MI I32:$Rt, 0, Value:$Vs)>;
144-
def: Pat<(Store Value:$Vs, (add I32:$Rt, ImmPred:$s)),
145-
(MI I32:$Rt, imm:$s, Value:$Vs)>;
146180
}
147181

148-
let Predicates = [UseHVX] in {
149-
defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, IsVecOff, HVI8>;
150-
defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, IsVecOff, HVI16>;
151-
defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, IsVecOff, HVI32>;
152-
153-
defm: HvxSt_pat<V6_vS32b_ai, alignedstore, IsVecOff, HVI8>;
154-
defm: HvxSt_pat<V6_vS32b_ai, alignedstore, IsVecOff, HVI16>;
155-
defm: HvxSt_pat<V6_vS32b_ai, alignedstore, IsVecOff, HVI32>;
182+
multiclass HvxSt_pat<InstHexagon MI, PatFrag Store, PatFrag Value,
183+
PatFrag ImmPred> {
184+
defm: HvxStfi_pat<MI, Store, Value, ImmPred>;
185+
defm: HvxStgi_pat<MI, Store, Value, ImmPred>;
186+
}
156187

157-
defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, IsVecOff, HVI8>;
158-
defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, IsVecOff, HVI16>;
159-
defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, IsVecOff, HVI32>;
188+
let Predicates = [UseHVX] in {
189+
// alignedstore will match a non-temporal store as well, so try non-temporal
190+
// first.
191+
defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, HVI8, IsVecOff>;
192+
defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, HVI16, IsVecOff>;
193+
defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, HVI32, IsVecOff>;
194+
defm: HvxSt_pat<V6_vS32b_ai, alignedstore, HVI8, IsVecOff>;
195+
defm: HvxSt_pat<V6_vS32b_ai, alignedstore, HVI16, IsVecOff>;
196+
defm: HvxSt_pat<V6_vS32b_ai, alignedstore, HVI32, IsVecOff>;
197+
defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, HVI8, IsVecOff>;
198+
defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, HVI16, IsVecOff>;
199+
defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, HVI32, IsVecOff>;
160200
}
161201

162202
// Bitcasts between same-size vector types are no-ops, except for the

‎llvm/test/CodeGen/Hexagon/vec-align.ll

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2,11 +2,10 @@
22

33
; Make sure we generate stack alignment.
44
; CHECK: [[REG1:r[0-9]*]] = and(r29,#-64)
5-
; CHECK: = add([[REG1]],#128)
6-
; CHECK: = add([[REG1]],#64)
7-
; Make sure we do not generate another -64 off SP.
8-
; CHECK: vmem(
9-
; CHECK-NOT: r{{[0-9]*}} = add(r29,#-64)
5+
; CHECK: vmem([[REG1]]+#2) =
6+
; CHECK: vmem([[REG1]]+#1) =
7+
; CHECK: = vmem([[REG1]]+#2)
8+
; CHECK: = vmem([[REG1]]+#1)
109

1110
target triple = "hexagon"
1211

@@ -42,5 +41,5 @@ declare <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32>, <16 x i32>) #1
4241

4342
declare void @f2(...) #0
4443

45-
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
44+
attributes #0 = { nounwind "target-cpu"="hexagonv65" "target-features"="+hvxv65,+hvx-length64b" }
4645
attributes #1 = { nounwind readnone }

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