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[RISCV] Store/restore RISCVMachineFunctionInfo into MIR YAML file
RISCVMachineFunctionInfo has some fields like VarArgsFrameIndex and VarArgsSaveSize are calculated at ISel lowering stage, those info are not contained in MIR files, that cause test cases rely on those field can't not reproduce correctly by MIR dump files. This patch adding the MIR read/write for those fields. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D123178
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‎llvm/lib/Target/RISCV/CMakeLists.txt

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@@ -31,6 +31,7 @@ add_llvm_target(RISCVCodeGen
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RISCVISelDAGToDAG.cpp
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RISCVISelLowering.cpp
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RISCVLegalizerInfo.cpp
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RISCVMachineFunctionInfo.cpp
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RISCVMCInstLower.cpp
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RISCVMergeBaseOffset.cpp
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RISCVRegisterBankInfo.cpp

‎llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp

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//=- RISCVMachineFunctionInfo.cpp - RISCV machine function info ---*- C++ -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares RISCV-specific per-machine-function information.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVMachineFunctionInfo.h"
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using namespace llvm;
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yaml::RISCVMachineFunctionInfo::RISCVMachineFunctionInfo(
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const llvm::RISCVMachineFunctionInfo &MFI)
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: VarArgsFrameIndex(MFI.getVarArgsFrameIndex()),
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VarArgsSaveSize(MFI.getVarArgsSaveSize()) {}
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void yaml::RISCVMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) {
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MappingTraits<RISCVMachineFunctionInfo>::mapping(YamlIO, *this);
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}
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void RISCVMachineFunctionInfo::initializeBaseYamlFields(
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const yaml::RISCVMachineFunctionInfo &YamlMFI) {
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VarArgsFrameIndex = YamlMFI.VarArgsFrameIndex;
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VarArgsSaveSize = YamlMFI.VarArgsSaveSize;
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}

‎llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h

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@@ -14,11 +14,34 @@
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#define LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H
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#include "RISCVSubtarget.h"
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#include "llvm/CodeGen/MIRYamlMapping.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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namespace llvm {
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class RISCVMachineFunctionInfo;
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namespace yaml {
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struct RISCVMachineFunctionInfo final : public yaml::MachineFunctionInfo {
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int VarArgsFrameIndex;
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int VarArgsSaveSize;
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RISCVMachineFunctionInfo() = default;
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RISCVMachineFunctionInfo(const llvm::RISCVMachineFunctionInfo &MFI);
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void mappingImpl(yaml::IO &YamlIO) override;
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~RISCVMachineFunctionInfo() = default;
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};
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template <> struct MappingTraits<RISCVMachineFunctionInfo> {
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static void mapping(IO &YamlIO, RISCVMachineFunctionInfo &MFI) {
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YamlIO.mapOptional("varArgsFrameIndex", MFI.VarArgsFrameIndex);
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YamlIO.mapOptional("varArgsSaveSize", MFI.VarArgsSaveSize);
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}
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};
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} // end namespace yaml
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/// RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo
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/// and contains private RISCV-specific information for each MachineFunction.
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class RISCVMachineFunctionInfo : public MachineFunctionInfo {
@@ -74,6 +97,8 @@ class RISCVMachineFunctionInfo : public MachineFunctionInfo {
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unsigned getCalleeSavedStackSize() const { return CalleeSavedStackSize; }
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void setCalleeSavedStackSize(unsigned Size) { CalleeSavedStackSize = Size; }
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void initializeBaseYamlFields(const yaml::RISCVMachineFunctionInfo &YamlMFI);
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};
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} // end namespace llvm

‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

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@@ -13,6 +13,7 @@
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#include "RISCVTargetMachine.h"
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#include "MCTargetDesc/RISCVBaseInfo.h"
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#include "RISCV.h"
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#include "RISCVMachineFunctionInfo.h"
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#include "RISCVTargetObjectFile.h"
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#include "RISCVTargetTransformInfo.h"
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#include "TargetInfo/RISCVTargetInfo.h"
@@ -22,6 +23,8 @@
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#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
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#include "llvm/CodeGen/GlobalISel/Legalizer.h"
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#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
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#include "llvm/CodeGen/MIRParser/MIParser.h"
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#include "llvm/CodeGen/MIRYamlMapping.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
@@ -208,3 +211,23 @@ void RISCVPassConfig::addPreRegAlloc() {
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addPass(createRISCVMergeBaseOffsetOptPass());
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addPass(createRISCVInsertVSETVLIPass());
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}
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yaml::MachineFunctionInfo *
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RISCVTargetMachine::createDefaultFuncInfoYAML() const {
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return new yaml::RISCVMachineFunctionInfo();
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}
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yaml::MachineFunctionInfo *
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RISCVTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
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const auto *MFI = MF.getInfo<RISCVMachineFunctionInfo>();
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return new yaml::RISCVMachineFunctionInfo(*MFI);
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}
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bool RISCVTargetMachine::parseMachineFunctionInfo(
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const yaml::MachineFunctionInfo &MFI, PerFunctionMIParsingState &PFS,
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SMDiagnostic &Error, SMRange &SourceRange) const {
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const auto &YamlMFI =
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static_cast<const yaml::RISCVMachineFunctionInfo &>(MFI);
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PFS.MF.getInfo<RISCVMachineFunctionInfo>()->initializeBaseYamlFields(YamlMFI);
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return false;
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}

‎llvm/lib/Target/RISCV/RISCVTargetMachine.h

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@@ -46,6 +46,14 @@ class RISCVTargetMachine : public LLVMTargetMachine {
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virtual bool isNoopAddrSpaceCast(unsigned SrcAS,
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unsigned DstAS) const override;
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yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;
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yaml::MachineFunctionInfo *
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convertFuncInfoToYAML(const MachineFunction &MF) const override;
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bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,
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PerFunctionMIParsingState &PFS,
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SMDiagnostic &Error,
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SMRange &SourceRange) const override;
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};
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} // namespace llvm
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‎llvm/test/CodeGen/MIR/RISCV/machine-function-info.mir

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# RUN: llc -mtriple=riscv64 -run-pass none %s -o - | FileCheck %s
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--- |
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; ModuleID = 'foo.ll'
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source_filename = "foo.ll"
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target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
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target triple = "riscv64"
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define void @foo(i32 %0, ...) {
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ret void
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}
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...
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---
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name: foo
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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failsVerification: false
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tracksDebugUserValues: false
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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- { id: 2, class: gpr, preferred-register: '' }
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- { id: 3, class: gpr, preferred-register: '' }
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- { id: 4, class: gpr, preferred-register: '' }
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- { id: 5, class: gpr, preferred-register: '' }
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- { id: 6, class: gpr, preferred-register: '' }
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- { id: 7, class: gpr, preferred-register: '' }
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liveins:
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- { reg: '$x11', virtual-reg: '%1' }
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- { reg: '$x12', virtual-reg: '%2' }
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- { reg: '$x13', virtual-reg: '%3' }
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- { reg: '$x14', virtual-reg: '%4' }
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- { reg: '$x15', virtual-reg: '%5' }
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- { reg: '$x16', virtual-reg: '%6' }
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- { reg: '$x17', virtual-reg: '%7' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 1
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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hasTailCall: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack:
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- { id: 0, type: default, offset: -8, size: 8, alignment: 8, stack-id: default,
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isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, type: default, offset: -16, size: 8, alignment: 16, stack-id: default,
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isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 2, type: default, offset: -24, size: 8, alignment: 8, stack-id: default,
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isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 3, type: default, offset: -32, size: 8, alignment: 16, stack-id: default,
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isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 4, type: default, offset: -40, size: 8, alignment: 8, stack-id: default,
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isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 5, type: default, offset: -48, size: 8, alignment: 16, stack-id: default,
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isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 6, type: default, offset: -56, size: 8, alignment: 8, stack-id: default,
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isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 7, type: default, offset: -64, size: 8, alignment: 16, stack-id: default,
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isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 8, type: default, offset: -56, size: 8, alignment: 8, stack-id: default,
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isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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stack: []
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callSites: []
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debugValueSubstitutions: []
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constants: []
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machineFunctionInfo:
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varArgsFrameIndex: -1
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varArgsSaveSize: 64
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body: |
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bb.0 (%ir-block.1):
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liveins: $x11, $x12, $x13, $x14, $x15, $x16, $x17
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; CHECK-LABEL: name: foo
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; CHECK: machineFunctionInfo:
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; CHECK-NEXT: varArgsFrameIndex: -1
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; CHECK-NEXT: varArgsSaveSize: 64
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; CHECK: liveins: $x11, $x12, $x13, $x14, $x15, $x16, $x17
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x17
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x16
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x15
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x14
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x13
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; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr = COPY $x12
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; CHECK-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY $x11
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; CHECK-NEXT: SD [[COPY]], %fixed-stack.8, 0 :: (store (s64))
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; CHECK-NEXT: SD [[COPY1]], %fixed-stack.7, 0 :: (store (s64) into %fixed-stack.7, align 16)
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; CHECK-NEXT: SD [[COPY2]], %fixed-stack.6, 0 :: (store (s64))
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; CHECK-NEXT: SD [[COPY3]], %fixed-stack.5, 0 :: (store (s64) into %fixed-stack.5, align 16)
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; CHECK-NEXT: SD [[COPY4]], %fixed-stack.4, 0 :: (store (s64))
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; CHECK-NEXT: SD [[COPY5]], %fixed-stack.3, 0 :: (store (s64) into %fixed-stack.3, align 16)
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; CHECK-NEXT: SD [[COPY6]], %fixed-stack.2, 0 :: (store (s64))
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; CHECK-NEXT: PseudoRET
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%7:gpr = COPY $x17
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%6:gpr = COPY $x16
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%5:gpr = COPY $x15
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%4:gpr = COPY $x14
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%3:gpr = COPY $x13
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%2:gpr = COPY $x12
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%1:gpr = COPY $x11
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SD %7, %fixed-stack.0, 0 :: (store (s64))
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SD %6, %fixed-stack.1, 0 :: (store (s64) into %fixed-stack.1, align 16)
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SD %5, %fixed-stack.2, 0 :: (store (s64))
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SD %4, %fixed-stack.3, 0 :: (store (s64) into %fixed-stack.3, align 16)
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SD %3, %fixed-stack.4, 0 :: (store (s64))
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SD %2, %fixed-stack.5, 0 :: (store (s64) into %fixed-stack.5, align 16)
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SD %1, %fixed-stack.6, 0 :: (store (s64))
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PseudoRET
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...

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