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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| 2 | +; RUN: llc -mtriple=riscv32 -verify-machineinstrs -no-integrated-as < %s \ |
| 3 | +; RUN: | FileCheck -check-prefixes=RV32I %s |
| 4 | +; RUN: llc -mtriple=riscv64 -verify-machineinstrs -no-integrated-as < %s \ |
| 5 | +; RUN: | FileCheck -check-prefixes=RV64I %s |
| 6 | +; RUN: llc -mtriple=riscv32 -code-model=medium -verify-machineinstrs -no-integrated-as < %s \ |
| 7 | +; RUN: | FileCheck -check-prefixes=RV32I-MEDIUM %s |
| 8 | +; RUN: llc -mtriple=riscv64 -code-model=medium -verify-machineinstrs -no-integrated-as < %s \ |
| 9 | +; RUN: | FileCheck -check-prefixes=RV64I-MEDIUM %s |
| 10 | + |
| 11 | +define void @constraint_m_1(ptr %a) nounwind { |
| 12 | +; RV32I-LABEL: constraint_m_1: |
| 13 | +; RV32I: # %bb.0: |
| 14 | +; RV32I-NEXT: #APP |
| 15 | +; RV32I-NEXT: #NO_APP |
| 16 | +; RV32I-NEXT: ret |
| 17 | +; |
| 18 | +; RV64I-LABEL: constraint_m_1: |
| 19 | +; RV64I: # %bb.0: |
| 20 | +; RV64I-NEXT: #APP |
| 21 | +; RV64I-NEXT: #NO_APP |
| 22 | +; RV64I-NEXT: ret |
| 23 | +; |
| 24 | +; RV32I-MEDIUM-LABEL: constraint_m_1: |
| 25 | +; RV32I-MEDIUM: # %bb.0: |
| 26 | +; RV32I-MEDIUM-NEXT: #APP |
| 27 | +; RV32I-MEDIUM-NEXT: #NO_APP |
| 28 | +; RV32I-MEDIUM-NEXT: ret |
| 29 | +; |
| 30 | +; RV64I-MEDIUM-LABEL: constraint_m_1: |
| 31 | +; RV64I-MEDIUM: # %bb.0: |
| 32 | +; RV64I-MEDIUM-NEXT: #APP |
| 33 | +; RV64I-MEDIUM-NEXT: #NO_APP |
| 34 | +; RV64I-MEDIUM-NEXT: ret |
| 35 | + call void asm sideeffect "", "=*m"(ptr elementtype(i32) %a) |
| 36 | + ret void |
| 37 | +} |
| 38 | + |
| 39 | +define i32 @constraint_m_2(ptr %a) nounwind { |
| 40 | +; RV32I-LABEL: constraint_m_2: |
| 41 | +; RV32I: # %bb.0: |
| 42 | +; RV32I-NEXT: #APP |
| 43 | +; RV32I-NEXT: lw a0, 0(a0) |
| 44 | +; RV32I-NEXT: #NO_APP |
| 45 | +; RV32I-NEXT: ret |
| 46 | +; |
| 47 | +; RV64I-LABEL: constraint_m_2: |
| 48 | +; RV64I: # %bb.0: |
| 49 | +; RV64I-NEXT: #APP |
| 50 | +; RV64I-NEXT: lw a0, 0(a0) |
| 51 | +; RV64I-NEXT: #NO_APP |
| 52 | +; RV64I-NEXT: ret |
| 53 | +; |
| 54 | +; RV32I-MEDIUM-LABEL: constraint_m_2: |
| 55 | +; RV32I-MEDIUM: # %bb.0: |
| 56 | +; RV32I-MEDIUM-NEXT: #APP |
| 57 | +; RV32I-MEDIUM-NEXT: lw a0, 0(a0) |
| 58 | +; RV32I-MEDIUM-NEXT: #NO_APP |
| 59 | +; RV32I-MEDIUM-NEXT: ret |
| 60 | +; |
| 61 | +; RV64I-MEDIUM-LABEL: constraint_m_2: |
| 62 | +; RV64I-MEDIUM: # %bb.0: |
| 63 | +; RV64I-MEDIUM-NEXT: #APP |
| 64 | +; RV64I-MEDIUM-NEXT: lw a0, 0(a0) |
| 65 | +; RV64I-MEDIUM-NEXT: #NO_APP |
| 66 | +; RV64I-MEDIUM-NEXT: ret |
| 67 | + %1 = tail call i32 asm "lw $0, $1", "=r,*m"(ptr elementtype(i32) %a) |
| 68 | + ret i32 %1 |
| 69 | +} |
| 70 | + |
| 71 | +define i32 @constraint_m_with_offset(ptr %a) nounwind { |
| 72 | +; RV32I-LABEL: constraint_m_with_offset: |
| 73 | +; RV32I: # %bb.0: |
| 74 | +; RV32I-NEXT: #APP |
| 75 | +; RV32I-NEXT: lw a0, 4(a0) |
| 76 | +; RV32I-NEXT: #NO_APP |
| 77 | +; RV32I-NEXT: ret |
| 78 | +; |
| 79 | +; RV64I-LABEL: constraint_m_with_offset: |
| 80 | +; RV64I: # %bb.0: |
| 81 | +; RV64I-NEXT: #APP |
| 82 | +; RV64I-NEXT: lw a0, 4(a0) |
| 83 | +; RV64I-NEXT: #NO_APP |
| 84 | +; RV64I-NEXT: ret |
| 85 | +; |
| 86 | +; RV32I-MEDIUM-LABEL: constraint_m_with_offset: |
| 87 | +; RV32I-MEDIUM: # %bb.0: |
| 88 | +; RV32I-MEDIUM-NEXT: #APP |
| 89 | +; RV32I-MEDIUM-NEXT: lw a0, 4(a0) |
| 90 | +; RV32I-MEDIUM-NEXT: #NO_APP |
| 91 | +; RV32I-MEDIUM-NEXT: ret |
| 92 | +; |
| 93 | +; RV64I-MEDIUM-LABEL: constraint_m_with_offset: |
| 94 | +; RV64I-MEDIUM: # %bb.0: |
| 95 | +; RV64I-MEDIUM-NEXT: #APP |
| 96 | +; RV64I-MEDIUM-NEXT: lw a0, 4(a0) |
| 97 | +; RV64I-MEDIUM-NEXT: #NO_APP |
| 98 | +; RV64I-MEDIUM-NEXT: ret |
| 99 | + %1 = getelementptr i32, ptr %a, i32 1 |
| 100 | + %2 = tail call i32 asm "lw $0, $1", "=r,*m"(ptr elementtype(i32) %1) |
| 101 | + ret i32 %2 |
| 102 | +} |
| 103 | + |
| 104 | +define void @constraint_o_1(ptr %a) nounwind { |
| 105 | +; RV32I-LABEL: constraint_o_1: |
| 106 | +; RV32I: # %bb.0: |
| 107 | +; RV32I-NEXT: #APP |
| 108 | +; RV32I-NEXT: #NO_APP |
| 109 | +; RV32I-NEXT: ret |
| 110 | +; |
| 111 | +; RV64I-LABEL: constraint_o_1: |
| 112 | +; RV64I: # %bb.0: |
| 113 | +; RV64I-NEXT: #APP |
| 114 | +; RV64I-NEXT: #NO_APP |
| 115 | +; RV64I-NEXT: ret |
| 116 | +; |
| 117 | +; RV32I-MEDIUM-LABEL: constraint_o_1: |
| 118 | +; RV32I-MEDIUM: # %bb.0: |
| 119 | +; RV32I-MEDIUM-NEXT: #APP |
| 120 | +; RV32I-MEDIUM-NEXT: #NO_APP |
| 121 | +; RV32I-MEDIUM-NEXT: ret |
| 122 | +; |
| 123 | +; RV64I-MEDIUM-LABEL: constraint_o_1: |
| 124 | +; RV64I-MEDIUM: # %bb.0: |
| 125 | +; RV64I-MEDIUM-NEXT: #APP |
| 126 | +; RV64I-MEDIUM-NEXT: #NO_APP |
| 127 | +; RV64I-MEDIUM-NEXT: ret |
| 128 | + call void asm sideeffect "", "=*o"(ptr elementtype(i32) %a) |
| 129 | + ret void |
| 130 | +} |
| 131 | + |
| 132 | +define i32 @constraint_o_2(ptr %a) nounwind { |
| 133 | +; RV32I-LABEL: constraint_o_2: |
| 134 | +; RV32I: # %bb.0: |
| 135 | +; RV32I-NEXT: #APP |
| 136 | +; RV32I-NEXT: lw a0, 0(a0) |
| 137 | +; RV32I-NEXT: #NO_APP |
| 138 | +; RV32I-NEXT: ret |
| 139 | +; |
| 140 | +; RV64I-LABEL: constraint_o_2: |
| 141 | +; RV64I: # %bb.0: |
| 142 | +; RV64I-NEXT: #APP |
| 143 | +; RV64I-NEXT: lw a0, 0(a0) |
| 144 | +; RV64I-NEXT: #NO_APP |
| 145 | +; RV64I-NEXT: ret |
| 146 | +; |
| 147 | +; RV32I-MEDIUM-LABEL: constraint_o_2: |
| 148 | +; RV32I-MEDIUM: # %bb.0: |
| 149 | +; RV32I-MEDIUM-NEXT: #APP |
| 150 | +; RV32I-MEDIUM-NEXT: lw a0, 0(a0) |
| 151 | +; RV32I-MEDIUM-NEXT: #NO_APP |
| 152 | +; RV32I-MEDIUM-NEXT: ret |
| 153 | +; |
| 154 | +; RV64I-MEDIUM-LABEL: constraint_o_2: |
| 155 | +; RV64I-MEDIUM: # %bb.0: |
| 156 | +; RV64I-MEDIUM-NEXT: #APP |
| 157 | +; RV64I-MEDIUM-NEXT: lw a0, 0(a0) |
| 158 | +; RV64I-MEDIUM-NEXT: #NO_APP |
| 159 | +; RV64I-MEDIUM-NEXT: ret |
| 160 | + %1 = tail call i32 asm "lw $0, $1", "=r,*o"(ptr elementtype(i32) %a) |
| 161 | + ret i32 %1 |
| 162 | +} |
| 163 | + |
| 164 | +define i32 @constraint_o_with_offset(ptr %a) nounwind { |
| 165 | +; RV32I-LABEL: constraint_o_with_offset: |
| 166 | +; RV32I: # %bb.0: |
| 167 | +; RV32I-NEXT: #APP |
| 168 | +; RV32I-NEXT: lw a0, 4(a0) |
| 169 | +; RV32I-NEXT: #NO_APP |
| 170 | +; RV32I-NEXT: ret |
| 171 | +; |
| 172 | +; RV64I-LABEL: constraint_o_with_offset: |
| 173 | +; RV64I: # %bb.0: |
| 174 | +; RV64I-NEXT: #APP |
| 175 | +; RV64I-NEXT: lw a0, 4(a0) |
| 176 | +; RV64I-NEXT: #NO_APP |
| 177 | +; RV64I-NEXT: ret |
| 178 | +; |
| 179 | +; RV32I-MEDIUM-LABEL: constraint_o_with_offset: |
| 180 | +; RV32I-MEDIUM: # %bb.0: |
| 181 | +; RV32I-MEDIUM-NEXT: #APP |
| 182 | +; RV32I-MEDIUM-NEXT: lw a0, 4(a0) |
| 183 | +; RV32I-MEDIUM-NEXT: #NO_APP |
| 184 | +; RV32I-MEDIUM-NEXT: ret |
| 185 | +; |
| 186 | +; RV64I-MEDIUM-LABEL: constraint_o_with_offset: |
| 187 | +; RV64I-MEDIUM: # %bb.0: |
| 188 | +; RV64I-MEDIUM-NEXT: #APP |
| 189 | +; RV64I-MEDIUM-NEXT: lw a0, 4(a0) |
| 190 | +; RV64I-MEDIUM-NEXT: #NO_APP |
| 191 | +; RV64I-MEDIUM-NEXT: ret |
| 192 | + %1 = getelementptr i32, ptr %a, i32 1 |
| 193 | + %2 = tail call i32 asm "lw $0, $1", "=r,*o"(ptr elementtype(i32) %1) |
| 194 | + ret i32 %2 |
| 195 | +} |
| 196 | + |
| 197 | +define void @constraint_A(ptr %a) nounwind { |
| 198 | +; RV32I-LABEL: constraint_A: |
| 199 | +; RV32I: # %bb.0: |
| 200 | +; RV32I-NEXT: #APP |
| 201 | +; RV32I-NEXT: sb s0, 0(a0) |
| 202 | +; RV32I-NEXT: #NO_APP |
| 203 | +; RV32I-NEXT: #APP |
| 204 | +; RV32I-NEXT: lb s1, 0(a0) |
| 205 | +; RV32I-NEXT: #NO_APP |
| 206 | +; RV32I-NEXT: ret |
| 207 | +; |
| 208 | +; RV64I-LABEL: constraint_A: |
| 209 | +; RV64I: # %bb.0: |
| 210 | +; RV64I-NEXT: #APP |
| 211 | +; RV64I-NEXT: sb s0, 0(a0) |
| 212 | +; RV64I-NEXT: #NO_APP |
| 213 | +; RV64I-NEXT: #APP |
| 214 | +; RV64I-NEXT: lb s1, 0(a0) |
| 215 | +; RV64I-NEXT: #NO_APP |
| 216 | +; RV64I-NEXT: ret |
| 217 | +; |
| 218 | +; RV32I-MEDIUM-LABEL: constraint_A: |
| 219 | +; RV32I-MEDIUM: # %bb.0: |
| 220 | +; RV32I-MEDIUM-NEXT: #APP |
| 221 | +; RV32I-MEDIUM-NEXT: sb s0, 0(a0) |
| 222 | +; RV32I-MEDIUM-NEXT: #NO_APP |
| 223 | +; RV32I-MEDIUM-NEXT: #APP |
| 224 | +; RV32I-MEDIUM-NEXT: lb s1, 0(a0) |
| 225 | +; RV32I-MEDIUM-NEXT: #NO_APP |
| 226 | +; RV32I-MEDIUM-NEXT: ret |
| 227 | +; |
| 228 | +; RV64I-MEDIUM-LABEL: constraint_A: |
| 229 | +; RV64I-MEDIUM: # %bb.0: |
| 230 | +; RV64I-MEDIUM-NEXT: #APP |
| 231 | +; RV64I-MEDIUM-NEXT: sb s0, 0(a0) |
| 232 | +; RV64I-MEDIUM-NEXT: #NO_APP |
| 233 | +; RV64I-MEDIUM-NEXT: #APP |
| 234 | +; RV64I-MEDIUM-NEXT: lb s1, 0(a0) |
| 235 | +; RV64I-MEDIUM-NEXT: #NO_APP |
| 236 | +; RV64I-MEDIUM-NEXT: ret |
| 237 | + tail call void asm sideeffect "sb s0, $0", "*A"(ptr elementtype(i8) %a) |
| 238 | + tail call void asm sideeffect "lb s1, $0", "*A"(ptr elementtype(i8) %a) |
| 239 | + ret void |
| 240 | +} |
| 241 | + |
| 242 | +define i32 @constraint_A_with_offset(ptr %a) nounwind { |
| 243 | +; RV32I-LABEL: constraint_A_with_offset: |
| 244 | +; RV32I: # %bb.0: |
| 245 | +; RV32I-NEXT: addi a0, a0, 4 |
| 246 | +; RV32I-NEXT: #APP |
| 247 | +; RV32I-NEXT: lw a0, 0(a0) |
| 248 | +; RV32I-NEXT: #NO_APP |
| 249 | +; RV32I-NEXT: ret |
| 250 | +; |
| 251 | +; RV64I-LABEL: constraint_A_with_offset: |
| 252 | +; RV64I: # %bb.0: |
| 253 | +; RV64I-NEXT: addi a0, a0, 4 |
| 254 | +; RV64I-NEXT: #APP |
| 255 | +; RV64I-NEXT: lw a0, 0(a0) |
| 256 | +; RV64I-NEXT: #NO_APP |
| 257 | +; RV64I-NEXT: ret |
| 258 | +; |
| 259 | +; RV32I-MEDIUM-LABEL: constraint_A_with_offset: |
| 260 | +; RV32I-MEDIUM: # %bb.0: |
| 261 | +; RV32I-MEDIUM-NEXT: addi a0, a0, 4 |
| 262 | +; RV32I-MEDIUM-NEXT: #APP |
| 263 | +; RV32I-MEDIUM-NEXT: lw a0, 0(a0) |
| 264 | +; RV32I-MEDIUM-NEXT: #NO_APP |
| 265 | +; RV32I-MEDIUM-NEXT: ret |
| 266 | +; |
| 267 | +; RV64I-MEDIUM-LABEL: constraint_A_with_offset: |
| 268 | +; RV64I-MEDIUM: # %bb.0: |
| 269 | +; RV64I-MEDIUM-NEXT: addi a0, a0, 4 |
| 270 | +; RV64I-MEDIUM-NEXT: #APP |
| 271 | +; RV64I-MEDIUM-NEXT: lw a0, 0(a0) |
| 272 | +; RV64I-MEDIUM-NEXT: #NO_APP |
| 273 | +; RV64I-MEDIUM-NEXT: ret |
| 274 | + %1 = getelementptr i32, ptr %a, i32 1 |
| 275 | + %2 = tail call i32 asm "lw $0, $1", "=r,*A"(ptr elementtype(i32) %1) |
| 276 | + ret i32 %2 |
| 277 | +} |
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