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kazutakahiratakazutakahirata
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[CodeGen] Construct SmallVector with ArrayRef (NFC) (llvm#101841)
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14 files changed

+27
-33
lines changed

14 files changed

+27
-33
lines changed

‎llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ class CallLowering {
5454
BaseArgInfo(Type *Ty,
5555
ArrayRef<ISD::ArgFlagsTy> Flags = ArrayRef<ISD::ArgFlagsTy>(),
5656
bool IsFixed = true)
57-
: Ty(Ty), Flags(Flags.begin(), Flags.end()), IsFixed(IsFixed) {}
57+
: Ty(Ty), Flags(Flags), IsFixed(IsFixed) {}
5858

5959
BaseArgInfo() : Ty(nullptr), IsFixed(false) {}
6060
};
@@ -81,8 +81,8 @@ class CallLowering {
8181
ArgInfo(ArrayRef<Register> Regs, Type *Ty, unsigned OrigIndex,
8282
ArrayRef<ISD::ArgFlagsTy> Flags = ArrayRef<ISD::ArgFlagsTy>(),
8383
bool IsFixed = true, const Value *OrigValue = nullptr)
84-
: BaseArgInfo(Ty, Flags, IsFixed), Regs(Regs.begin(), Regs.end()),
85-
OrigValue(OrigValue), OrigArgIndex(OrigIndex) {
84+
: BaseArgInfo(Ty, Flags, IsFixed), Regs(Regs), OrigValue(OrigValue),
85+
OrigArgIndex(OrigIndex) {
8686
if (!Regs.empty() && Flags.empty())
8787
this->Flags.push_back(ISD::ArgFlagsTy());
8888
// FIXME: We should have just one way of saying "no register".

‎llvm/include/llvm/CodeGen/GlobalISel/GISelChangeObserver.h

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -69,8 +69,7 @@ class GISelObserverWrapper : public MachineFunction::Delegate,
6969

7070
public:
7171
GISelObserverWrapper() = default;
72-
GISelObserverWrapper(ArrayRef<GISelChangeObserver *> Obs)
73-
: Observers(Obs.begin(), Obs.end()) {}
72+
GISelObserverWrapper(ArrayRef<GISelChangeObserver *> Obs) : Observers(Obs) {}
7473
// Adds an observer.
7574
void addObserver(GISelChangeObserver *O) { Observers.push_back(O); }
7675
// Removes an observer from the list and does nothing if observer is not

‎llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -136,7 +136,7 @@ class AppleAccelTableWriter : public AccelTableWriter {
136136
const SmallVector<Atom, 4> Atoms;
137137

138138
HeaderData(ArrayRef<Atom> AtomList, uint32_t Offset = 0)
139-
: DieOffsetBase(Offset), Atoms(AtomList.begin(), AtomList.end()) {}
139+
: DieOffsetBase(Offset), Atoms(AtomList) {}
140140

141141
void emit(AsmPrinter *Asm) const;
142142
#ifndef NDEBUG

‎llvm/lib/CodeGen/AsmPrinter/DebugLocEntry.h

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -118,13 +118,11 @@ class DbgValueLoc {
118118

119119
public:
120120
DbgValueLoc(const DIExpression *Expr, ArrayRef<DbgValueLocEntry> Locs)
121-
: Expression(Expr), ValueLocEntries(Locs.begin(), Locs.end()),
122-
IsVariadic(true) {}
121+
: Expression(Expr), ValueLocEntries(Locs), IsVariadic(true) {}
123122

124123
DbgValueLoc(const DIExpression *Expr, ArrayRef<DbgValueLocEntry> Locs,
125124
bool IsVariadic)
126-
: Expression(Expr), ValueLocEntries(Locs.begin(), Locs.end()),
127-
IsVariadic(IsVariadic) {
125+
: Expression(Expr), ValueLocEntries(Locs), IsVariadic(IsVariadic) {
128126
#ifndef NDEBUG
129127
assert(Expr->isValid() ||
130128
!any_of(Locs, [](auto LE) { return LE.isLocation(); }));

‎llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -436,7 +436,7 @@ static void buildCopyFromRegs(MachineIRBuilder &B, ArrayRef<Register> OrigRegs,
436436

437437
if (PartLLT.isVector()) {
438438
assert(OrigRegs.size() == 1);
439-
SmallVector<Register> CastRegs(Regs.begin(), Regs.end());
439+
SmallVector<Register> CastRegs(Regs);
440440

441441
// If PartLLT is a mismatched vector in both number of elements and element
442442
// size, e.g. PartLLT == v2s64 and LLTy is v3s32, then first coerce it to

‎llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -646,7 +646,7 @@ MachineInstrBuilder MachineIRBuilder::buildMergeValues(const DstOp &Res,
646646
// Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>,
647647
// we need some temporary storage for the DstOp objects. Here we use a
648648
// sufficiently large SmallVector to not go through the heap.
649-
SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
649+
SmallVector<SrcOp, 8> TmpVec(Ops);
650650
assert(TmpVec.size() > 1);
651651
return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);
652652
}
@@ -657,7 +657,7 @@ MachineIRBuilder::buildMergeLikeInstr(const DstOp &Res,
657657
// Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>,
658658
// we need some temporary storage for the DstOp objects. Here we use a
659659
// sufficiently large SmallVector to not go through the heap.
660-
SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
660+
SmallVector<SrcOp, 8> TmpVec(Ops);
661661
assert(TmpVec.size() > 1);
662662
return buildInstr(getOpcodeForMerge(Res, TmpVec), Res, TmpVec);
663663
}
@@ -685,7 +685,7 @@ MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<LLT> Res,
685685
// Unfortunately to convert from ArrayRef<LLT> to ArrayRef<DstOp>,
686686
// we need some temporary storage for the DstOp objects. Here we use a
687687
// sufficiently large SmallVector to not go through the heap.
688-
SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
688+
SmallVector<DstOp, 8> TmpVec(Res);
689689
assert(TmpVec.size() > 1);
690690
return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
691691
}
@@ -702,7 +702,7 @@ MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<Register> Res,
702702
// Unfortunately to convert from ArrayRef<Register> to ArrayRef<DstOp>,
703703
// we need some temporary storage for the DstOp objects. Here we use a
704704
// sufficiently large SmallVector to not go through the heap.
705-
SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
705+
SmallVector<DstOp, 8> TmpVec(Res);
706706
assert(TmpVec.size() > 1);
707707
return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
708708
}
@@ -712,7 +712,7 @@ MachineInstrBuilder MachineIRBuilder::buildBuildVector(const DstOp &Res,
712712
// Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
713713
// we need some temporary storage for the DstOp objects. Here we use a
714714
// sufficiently large SmallVector to not go through the heap.
715-
SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
715+
SmallVector<SrcOp, 8> TmpVec(Ops);
716716
return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
717717
}
718718

@@ -739,7 +739,7 @@ MachineIRBuilder::buildBuildVectorTrunc(const DstOp &Res,
739739
// Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
740740
// we need some temporary storage for the DstOp objects. Here we use a
741741
// sufficiently large SmallVector to not go through the heap.
742-
SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
742+
SmallVector<SrcOp, 8> TmpVec(Ops);
743743
if (TmpVec[0].getLLTTy(*getMRI()).getSizeInBits() ==
744744
Res.getLLTTy(*getMRI()).getElementType().getSizeInBits())
745745
return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
@@ -789,7 +789,7 @@ MachineIRBuilder::buildConcatVectors(const DstOp &Res, ArrayRef<Register> Ops) {
789789
// Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
790790
// we need some temporary storage for the DstOp objects. Here we use a
791791
// sufficiently large SmallVector to not go through the heap.
792-
SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
792+
SmallVector<SrcOp, 8> TmpVec(Ops);
793793
return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);
794794
}
795795

‎llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -252,8 +252,7 @@ class TransferTracker {
252252
DbgValueProperties Properties;
253253
UseBeforeDef(ArrayRef<DbgOp> Values, DebugVariableID VarID,
254254
const DbgValueProperties &Properties)
255-
: Values(Values.begin(), Values.end()), VarID(VarID),
256-
Properties(Properties) {}
255+
: Values(Values), VarID(VarID), Properties(Properties) {}
257256
};
258257

259258
/// Map from instruction index (within the block) to the set of UseBeforeDefs

‎llvm/lib/CodeGen/LiveIntervals.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1681,7 +1681,7 @@ LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB,
16811681
Indexes->repairIndexesInRange(MBB, Begin, End);
16821682

16831683
// Make sure a live interval exists for all register operands in the range.
1684-
SmallVector<Register> RegsToRepair(OrigRegs.begin(), OrigRegs.end());
1684+
SmallVector<Register> RegsToRepair(OrigRegs);
16851685
for (MachineBasicBlock::iterator I = End; I != Begin;) {
16861686
--I;
16871687
MachineInstr &MI = *I;

‎llvm/lib/CodeGen/MachineScheduler.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1742,8 +1742,8 @@ class BaseMemOpClusterMutation : public ScheduleDAGMutation {
17421742

17431743
MemOpInfo(SUnit *SU, ArrayRef<const MachineOperand *> BaseOps,
17441744
int64_t Offset, bool OffsetIsScalable, LocationSize Width)
1745-
: SU(SU), BaseOps(BaseOps.begin(), BaseOps.end()), Offset(Offset),
1746-
Width(Width), OffsetIsScalable(OffsetIsScalable) {}
1745+
: SU(SU), BaseOps(BaseOps), Offset(Offset), Width(Width),
1746+
OffsetIsScalable(OffsetIsScalable) {}
17471747

17481748
static bool Compare(const MachineOperand *const &A,
17491749
const MachineOperand *const &B) {

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -25241,7 +25241,7 @@ static SDValue combineShuffleToZeroExtendVectorInReg(ShuffleVectorSDNode *SVN,
2524125241
if (!VT.isInteger() || IsBigEndian)
2524225242
return SDValue();
2524325243

25244-
SmallVector<int, 16> Mask(SVN->getMask().begin(), SVN->getMask().end());
25244+
SmallVector<int, 16> Mask(SVN->getMask());
2524525245
auto ForEachDecomposedIndice = [NumElts, &Mask](auto Fn) {
2524625246
for (int &Indice : Mask) {
2524725247
if (Indice < 0)
@@ -25444,8 +25444,7 @@ static SDValue combineShuffleOfSplatVal(ShuffleVectorSDNode *Shuf,
2544425444
if (!MinNonUndefIdx)
2544525445
return DAG.getUNDEF(VT); // All undef - result is undef.
2544625446
assert(*MinNonUndefIdx < NumElts && "Expected valid element index.");
25447-
SmallVector<int, 8> SplatMask(Shuf->getMask().begin(),
25448-
Shuf->getMask().end());
25447+
SmallVector<int, 8> SplatMask(Shuf->getMask());
2544925448
for (int &Idx : SplatMask) {
2545025449
if (Idx < 0)
2545125450
continue; // Passthrough sentinel indices.

‎llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3577,7 +3577,7 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfOp_ATOMIC_STORE(SDNode *N,
35773577

35783578
SDValue DAGTypeLegalizer::SoftPromoteHalfOp_STACKMAP(SDNode *N, unsigned OpNo) {
35793579
assert(OpNo > 1); // Because the first two arguments are guaranteed legal.
3580-
SmallVector<SDValue> NewOps(N->ops().begin(), N->ops().end());
3580+
SmallVector<SDValue> NewOps(N->ops());
35813581
SDValue Op = N->getOperand(OpNo);
35823582
NewOps[OpNo] = GetSoftPromotedHalf(Op);
35833583
SDValue NewNode =
@@ -3592,7 +3592,7 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfOp_STACKMAP(SDNode *N, unsigned OpNo) {
35923592
SDValue DAGTypeLegalizer::SoftPromoteHalfOp_PATCHPOINT(SDNode *N,
35933593
unsigned OpNo) {
35943594
assert(OpNo >= 7);
3595-
SmallVector<SDValue> NewOps(N->ops().begin(), N->ops().end());
3595+
SmallVector<SDValue> NewOps(N->ops());
35963596
SDValue Op = N->getOperand(OpNo);
35973597
NewOps[OpNo] = GetSoftPromotedHalf(Op);
35983598
SDValue NewNode =

‎llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2704,7 +2704,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_SET_ROUNDING(SDNode *N) {
27042704

27052705
SDValue DAGTypeLegalizer::PromoteIntOp_STACKMAP(SDNode *N, unsigned OpNo) {
27062706
assert(OpNo > 1); // Because the first two arguments are guaranteed legal.
2707-
SmallVector<SDValue> NewOps(N->ops().begin(), N->ops().end());
2707+
SmallVector<SDValue> NewOps(N->ops());
27082708
SDValue Operand = N->getOperand(OpNo);
27092709
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), Operand.getValueType());
27102710
NewOps[OpNo] = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), NVT, Operand);
@@ -2713,7 +2713,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_STACKMAP(SDNode *N, unsigned OpNo) {
27132713

27142714
SDValue DAGTypeLegalizer::PromoteIntOp_PATCHPOINT(SDNode *N, unsigned OpNo) {
27152715
assert(OpNo >= 7);
2716-
SmallVector<SDValue> NewOps(N->ops().begin(), N->ops().end());
2716+
SmallVector<SDValue> NewOps(N->ops());
27172717
SDValue Operand = N->getOperand(OpNo);
27182718
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), Operand.getValueType());
27192719
NewOps[OpNo] = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), NVT, Operand);

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10032,7 +10032,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
1003210032

1003310033
// Copy from an SDUse array into an SDValue array for use with
1003410034
// the regular getNode logic.
10035-
SmallVector<SDValue, 8> NewOps(Ops.begin(), Ops.end());
10035+
SmallVector<SDValue, 8> NewOps(Ops);
1003610036
return getNode(Opcode, DL, VT, NewOps);
1003710037
}
1003810038

‎llvm/lib/CodeGen/ShrinkWrap.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -440,8 +440,7 @@ static bool
440440
isSaveReachableThroughClean(const MachineBasicBlock *SavePoint,
441441
ArrayRef<MachineBasicBlock *> CleanPreds) {
442442
DenseSet<const MachineBasicBlock *> Visited;
443-
SmallVector<MachineBasicBlock *, 4> Worklist(CleanPreds.begin(),
444-
CleanPreds.end());
443+
SmallVector<MachineBasicBlock *, 4> Worklist(CleanPreds);
445444
while (!Worklist.empty()) {
446445
MachineBasicBlock *CleanBB = Worklist.pop_back_val();
447446
if (CleanBB == SavePoint)

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