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Revert "[LegalizeTypes][VP] Add splitting and widening support for VP_FNEG."
This reverts commit ac93f95. Committed by accident.
1 parent 2f6c148 commit ab7a7cc

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+11
-197
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3 files changed

+11
-197
lines changed

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Lines changed: 11 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -995,7 +995,7 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
995995
case ISD::FLOG10:
996996
case ISD::FLOG2:
997997
case ISD::FNEARBYINT:
998-
case ISD::FNEG: case ISD::VP_FNEG:
998+
case ISD::FNEG:
999999
case ISD::FREEZE:
10001000
case ISD::ARITH_FENCE:
10011001
case ISD::FP_EXTEND:
@@ -2069,33 +2069,15 @@ void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
20692069
else
20702070
std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
20712071

2072-
const SDNodeFlags Flags = N->getFlags();
2073-
unsigned Opcode = N->getOpcode();
2074-
if (N->getNumOperands() <= 2) {
2075-
if (Opcode == ISD::FP_ROUND) {
2076-
Lo = DAG.getNode(Opcode, dl, LoVT, Lo, N->getOperand(1), Flags);
2077-
Hi = DAG.getNode(Opcode, dl, HiVT, Hi, N->getOperand(1), Flags);
2078-
} else {
2079-
Lo = DAG.getNode(Opcode, dl, LoVT, Lo, Flags);
2080-
Hi = DAG.getNode(Opcode, dl, HiVT, Hi, Flags);
2081-
}
2082-
return;
2072+
if (N->getOpcode() == ISD::FP_ROUND) {
2073+
Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1),
2074+
N->getFlags());
2075+
Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1),
2076+
N->getFlags());
2077+
} else {
2078+
Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getFlags());
2079+
Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getFlags());
20832080
}
2084-
2085-
assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
2086-
assert(N->isVPOpcode() && "Expected VP opcode");
2087-
2088-
SDValue MaskLo, MaskHi;
2089-
std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(1));
2090-
2091-
SDValue EVLLo, EVLHi;
2092-
std::tie(EVLLo, EVLHi) =
2093-
DAG.SplitEVL(N->getOperand(2), N->getValueType(0), dl);
2094-
2095-
Lo = DAG.getNode(Opcode, dl, Lo.getValueType(),
2096-
{Lo, MaskLo, EVLLo}, Flags);
2097-
Hi = DAG.getNode(Opcode, dl, Hi.getValueType(),
2098-
{Hi, MaskHi, EVLHi}, Flags);
20992081
}
21002082

21012083
void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo,
@@ -3435,7 +3417,7 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
34353417
case ISD::CTPOP:
34363418
case ISD::CTTZ:
34373419
case ISD::CTTZ_ZERO_UNDEF:
3438-
case ISD::FNEG: case ISD::VP_FNEG:
3420+
case ISD::FNEG:
34393421
case ISD::FREEZE:
34403422
case ISD::ARITH_FENCE:
34413423
case ISD::FCANONICALIZE:
@@ -4046,16 +4028,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
40464028
// Unary op widening.
40474029
EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
40484030
SDValue InOp = GetWidenedVector(N->getOperand(0));
4049-
if (N->getNumOperands() == 1)
4050-
return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp);
4051-
4052-
assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
4053-
assert(N->isVPOpcode() && "Expected VP opcode");
4054-
4055-
SDValue Mask =
4056-
GetWidenedMask(N->getOperand(1), WidenVT.getVectorElementCount());
4057-
return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT,
4058-
{InOp, Mask, N->getOperand(2)});
4031+
return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp);
40594032
}
40604033

40614034
SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll

Lines changed: 0 additions & 78 deletions
Original file line numberDiff line numberDiff line change
@@ -268,30 +268,6 @@ define <8 x double> @vfneg_vv_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl)
268268
ret <8 x double> %v
269269
}
270270

271-
declare <15 x double> @llvm.vp.fneg.v15f64(<15 x double>, <15 x i1>, i32)
272-
273-
define <15 x double> @vfneg_vv_v15f64(<15 x double> %va, <15 x i1> %m, i32 zeroext %evl) {
274-
; CHECK-LABEL: vfneg_vv_v15f64:
275-
; CHECK: # %bb.0:
276-
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
277-
; CHECK-NEXT: vfneg.v v8, v8, v0.t
278-
; CHECK-NEXT: ret
279-
%v = call <15 x double> @llvm.vp.fneg.v15f64(<15 x double> %va, <15 x i1> %m, i32 %evl)
280-
ret <15 x double> %v
281-
}
282-
283-
define <15 x double> @vfneg_vv_v15f64_unmasked(<15 x double> %va, i32 zeroext %evl) {
284-
; CHECK-LABEL: vfneg_vv_v15f64_unmasked:
285-
; CHECK: # %bb.0:
286-
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
287-
; CHECK-NEXT: vfsgnjn.vv v8, v8, v8
288-
; CHECK-NEXT: ret
289-
%head = insertelement <15 x i1> poison, i1 true, i32 0
290-
%m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer
291-
%v = call <15 x double> @llvm.vp.fneg.v15f64(<15 x double> %va, <15 x i1> %m, i32 %evl)
292-
ret <15 x double> %v
293-
}
294-
295271
declare <16 x double> @llvm.vp.fneg.v16f64(<16 x double>, <16 x i1>, i32)
296272

297273
define <16 x double> @vfneg_vv_v16f64(<16 x double> %va, <16 x i1> %m, i32 zeroext %evl) {
@@ -315,57 +291,3 @@ define <16 x double> @vfneg_vv_v16f64_unmasked(<16 x double> %va, i32 zeroext %e
315291
%v = call <16 x double> @llvm.vp.fneg.v16f64(<16 x double> %va, <16 x i1> %m, i32 %evl)
316292
ret <16 x double> %v
317293
}
318-
319-
declare <32 x double> @llvm.vp.fneg.v32f64(<32 x double>, <32 x i1>, i32)
320-
321-
define <32 x double> @vfneg_vv_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroext %evl) {
322-
; CHECK-LABEL: vfneg_vv_v32f64:
323-
; CHECK: # %bb.0:
324-
; CHECK-NEXT: vmv1r.v v24, v0
325-
; CHECK-NEXT: li a1, 0
326-
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
327-
; CHECK-NEXT: addi a2, a0, -16
328-
; CHECK-NEXT: vslidedown.vi v0, v0, 2
329-
; CHECK-NEXT: bltu a0, a2, .LBB26_2
330-
; CHECK-NEXT: # %bb.1:
331-
; CHECK-NEXT: mv a1, a2
332-
; CHECK-NEXT: .LBB26_2:
333-
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
334-
; CHECK-NEXT: li a1, 16
335-
; CHECK-NEXT: vfneg.v v16, v16, v0.t
336-
; CHECK-NEXT: bltu a0, a1, .LBB26_4
337-
; CHECK-NEXT: # %bb.3:
338-
; CHECK-NEXT: li a0, 16
339-
; CHECK-NEXT: .LBB26_4:
340-
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
341-
; CHECK-NEXT: vmv1r.v v0, v24
342-
; CHECK-NEXT: vfneg.v v8, v8, v0.t
343-
; CHECK-NEXT: ret
344-
%v = call <32 x double> @llvm.vp.fneg.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl)
345-
ret <32 x double> %v
346-
}
347-
348-
define <32 x double> @vfneg_vv_v32f64_unmasked(<32 x double> %va, i32 zeroext %evl) {
349-
; CHECK-LABEL: vfneg_vv_v32f64_unmasked:
350-
; CHECK: # %bb.0:
351-
; CHECK-NEXT: addi a1, a0, -16
352-
; CHECK-NEXT: li a2, 0
353-
; CHECK-NEXT: bltu a0, a1, .LBB27_2
354-
; CHECK-NEXT: # %bb.1:
355-
; CHECK-NEXT: mv a2, a1
356-
; CHECK-NEXT: .LBB27_2:
357-
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
358-
; CHECK-NEXT: li a1, 16
359-
; CHECK-NEXT: vfsgnjn.vv v16, v16, v16
360-
; CHECK-NEXT: bltu a0, a1, .LBB27_4
361-
; CHECK-NEXT: # %bb.3:
362-
; CHECK-NEXT: li a0, 16
363-
; CHECK-NEXT: .LBB27_4:
364-
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
365-
; CHECK-NEXT: vfsgnjn.vv v8, v8, v8
366-
; CHECK-NEXT: ret
367-
%head = insertelement <32 x i1> poison, i1 true, i32 0
368-
%m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer
369-
%v = call <32 x double> @llvm.vp.fneg.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl)
370-
ret <32 x double> %v
371-
}

‎llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll

Lines changed: 0 additions & 81 deletions
Original file line numberDiff line numberDiff line change
@@ -340,30 +340,6 @@ define <vscale x 4 x double> @vfneg_vv_nxv4f64_unmasked(<vscale x 4 x double> %v
340340
ret <vscale x 4 x double> %v
341341
}
342342

343-
declare <vscale x 7 x double> @llvm.vp.fneg.nxv7f64(<vscale x 7 x double>, <vscale x 7 x i1>, i32)
344-
345-
define <vscale x 7 x double> @vfneg_vv_nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {
346-
; CHECK-LABEL: vfneg_vv_nxv7f64:
347-
; CHECK: # %bb.0:
348-
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
349-
; CHECK-NEXT: vfneg.v v8, v8, v0.t
350-
; CHECK-NEXT: ret
351-
%v = call <vscale x 7 x double> @llvm.vp.fneg.nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> %m, i32 %evl)
352-
ret <vscale x 7 x double> %v
353-
}
354-
355-
define <vscale x 7 x double> @vfneg_vv_nxv7f64_unmasked(<vscale x 7 x double> %va, i32 zeroext %evl) {
356-
; CHECK-LABEL: vfneg_vv_nxv7f64_unmasked:
357-
; CHECK: # %bb.0:
358-
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
359-
; CHECK-NEXT: vfsgnjn.vv v8, v8, v8
360-
; CHECK-NEXT: ret
361-
%head = insertelement <vscale x 7 x i1> poison, i1 true, i32 0
362-
%m = shufflevector <vscale x 7 x i1> %head, <vscale x 7 x i1> poison, <vscale x 7 x i32> zeroinitializer
363-
%v = call <vscale x 7 x double> @llvm.vp.fneg.nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> %m, i32 %evl)
364-
ret <vscale x 7 x double> %v
365-
}
366-
367343
declare <vscale x 8 x double> @llvm.vp.fneg.nxv8f64(<vscale x 8 x double>, <vscale x 8 x i1>, i32)
368344

369345
define <vscale x 8 x double> @vfneg_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
@@ -387,60 +363,3 @@ define <vscale x 8 x double> @vfneg_vv_nxv8f64_unmasked(<vscale x 8 x double> %v
387363
%v = call <vscale x 8 x double> @llvm.vp.fneg.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> %m, i32 %evl)
388364
ret <vscale x 8 x double> %v
389365
}
390-
391-
; Test splitting.
392-
declare <vscale x 16 x double> @llvm.vp.fneg.nxv16f64(<vscale x 16 x double>, <vscale x 16 x i1>, i32)
393-
394-
define <vscale x 16 x double> @vfneg_vv_nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
395-
; CHECK-LABEL: vfneg_vv_nxv16f64:
396-
; CHECK: # %bb.0:
397-
; CHECK-NEXT: vmv1r.v v24, v0
398-
; CHECK-NEXT: li a2, 0
399-
; CHECK-NEXT: csrr a1, vlenb
400-
; CHECK-NEXT: srli a4, a1, 3
401-
; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, mu
402-
; CHECK-NEXT: sub a3, a0, a1
403-
; CHECK-NEXT: vslidedown.vx v0, v0, a4
404-
; CHECK-NEXT: bltu a0, a3, .LBB32_2
405-
; CHECK-NEXT: # %bb.1:
406-
; CHECK-NEXT: mv a2, a3
407-
; CHECK-NEXT: .LBB32_2:
408-
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
409-
; CHECK-NEXT: vfneg.v v16, v16, v0.t
410-
; CHECK-NEXT: bltu a0, a1, .LBB32_4
411-
; CHECK-NEXT: # %bb.3:
412-
; CHECK-NEXT: mv a0, a1
413-
; CHECK-NEXT: .LBB32_4:
414-
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
415-
; CHECK-NEXT: vmv1r.v v0, v24
416-
; CHECK-NEXT: vfneg.v v8, v8, v0.t
417-
; CHECK-NEXT: ret
418-
%v = call <vscale x 16 x double> @llvm.vp.fneg.nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 %evl)
419-
ret <vscale x 16 x double> %v
420-
}
421-
422-
define <vscale x 16 x double> @vfneg_vv_nxv16f64_unmasked(<vscale x 16 x double> %va, i32 zeroext %evl) {
423-
; CHECK-LABEL: vfneg_vv_nxv16f64_unmasked:
424-
; CHECK: # %bb.0:
425-
; CHECK-NEXT: csrr a1, vlenb
426-
; CHECK-NEXT: mv a2, a0
427-
; CHECK-NEXT: bltu a0, a1, .LBB33_2
428-
; CHECK-NEXT: # %bb.1:
429-
; CHECK-NEXT: mv a2, a1
430-
; CHECK-NEXT: .LBB33_2:
431-
; CHECK-NEXT: li a3, 0
432-
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
433-
; CHECK-NEXT: sub a1, a0, a1
434-
; CHECK-NEXT: vfsgnjn.vv v8, v8, v8
435-
; CHECK-NEXT: bltu a0, a1, .LBB33_4
436-
; CHECK-NEXT: # %bb.3:
437-
; CHECK-NEXT: mv a3, a1
438-
; CHECK-NEXT: .LBB33_4:
439-
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, mu
440-
; CHECK-NEXT: vfsgnjn.vv v16, v16, v16
441-
; CHECK-NEXT: ret
442-
%head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0
443-
%m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
444-
%v = call <vscale x 16 x double> @llvm.vp.fneg.nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 %evl)
445-
ret <vscale x 16 x double> %v
446-
}

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