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[AArch64] Regenerate dp1.ll test, NFC
The old check lines were not showing enough congtext to show issues. Regenerate the test with theua auto-check lines to be clearer.
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  • llvm/test/CodeGen/AArch64

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‎llvm/test/CodeGen/AArch64/dp1.ll

Lines changed: 199 additions & 91 deletions
Original file line numberDiff line numberDiff line change
@@ -1,150 +1,258 @@
1-
; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s
2-
; RUN: llc -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s --check-prefixes=FALLBACK,GISEL
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s --check-prefixes=CHECK,CHECK-SDAG
3+
; RUN: llc -global-isel -global-isel-abort=1 -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s --check-prefixes=CHECK,CHECK-GISEL
34

45
@var32 = global i32 0
56
@var64 = global i64 0
67

7-
; FALLBACK-NOT: remark{{.*}}rev_i32
88
define void @rev_i32() {
99
; CHECK-LABEL: rev_i32:
10-
; GISEL-LABEL: rev_i32:
11-
%val0_tmp = load i32, i32* @var32
12-
%val1_tmp = call i32 @llvm.bswap.i32(i32 %val0_tmp)
13-
; CHECK: rev {{w[0-9]+}}, {{w[0-9]+}}
14-
; GISEL: rev {{w[0-9]+}}, {{w[0-9]+}}
15-
store volatile i32 %val1_tmp, i32* @var32
16-
ret void
10+
; CHECK: // %bb.0:
11+
; CHECK-NEXT: adrp x8, :got:var32
12+
; CHECK-NEXT: ldr x8, [x8, :got_lo12:var32]
13+
; CHECK-NEXT: ldr w9, [x8]
14+
; CHECK-NEXT: rev w9, w9
15+
; CHECK-NEXT: str w9, [x8]
16+
; CHECK-NEXT: ret
17+
%val0_tmp = load i32, i32* @var32
18+
%val1_tmp = call i32 @llvm.bswap.i32(i32 %val0_tmp)
19+
store volatile i32 %val1_tmp, i32* @var32
20+
ret void
1721
}
1822

19-
; FALLBACK-NOT: remark{{.*}}rev_i64
2023
define void @rev_i64() {
2124
; CHECK-LABEL: rev_i64:
22-
; GISEL-LABEL: rev_i64:
23-
%val0_tmp = load i64, i64* @var64
24-
%val1_tmp = call i64 @llvm.bswap.i64(i64 %val0_tmp)
25-
; CHECK: rev {{x[0-9]+}}, {{x[0-9]+}}
26-
; GISEL: rev {{x[0-9]+}}, {{x[0-9]+}}
27-
store volatile i64 %val1_tmp, i64* @var64
28-
ret void
25+
; CHECK: // %bb.0:
26+
; CHECK-NEXT: adrp x8, :got:var64
27+
; CHECK-NEXT: ldr x8, [x8, :got_lo12:var64]
28+
; CHECK-NEXT: ldr x9, [x8]
29+
; CHECK-NEXT: rev x9, x9
30+
; CHECK-NEXT: str x9, [x8]
31+
; CHECK-NEXT: ret
32+
%val0_tmp = load i64, i64* @var64
33+
%val1_tmp = call i64 @llvm.bswap.i64(i64 %val0_tmp)
34+
store volatile i64 %val1_tmp, i64* @var64
35+
ret void
2936
}
3037

3138
define void @rev32_i64() {
3239
; CHECK-LABEL: rev32_i64:
33-
%val0_tmp = load i64, i64* @var64
34-
%val1_tmp = shl i64 %val0_tmp, 32
35-
%val5_tmp = sub i64 64, 32
36-
%val2_tmp = lshr i64 %val0_tmp, %val5_tmp
37-
%val3_tmp = or i64 %val1_tmp, %val2_tmp
38-
%val4_tmp = call i64 @llvm.bswap.i64(i64 %val3_tmp)
39-
; CHECK: rev32 {{x[0-9]+}}, {{x[0-9]+}}
40-
store volatile i64 %val4_tmp, i64* @var64
41-
ret void
40+
; CHECK: // %bb.0:
41+
; CHECK-NEXT: adrp x8, :got:var64
42+
; CHECK-NEXT: ldr x8, [x8, :got_lo12:var64]
43+
; CHECK-NEXT: ldr x9, [x8]
44+
; CHECK-NEXT: rev32 x9, x9
45+
; CHECK-NEXT: str x9, [x8]
46+
; CHECK-NEXT: ret
47+
%val0_tmp = load i64, i64* @var64
48+
%val1_tmp = shl i64 %val0_tmp, 32
49+
%val5_tmp = sub i64 64, 32
50+
%val2_tmp = lshr i64 %val0_tmp, %val5_tmp
51+
%val3_tmp = or i64 %val1_tmp, %val2_tmp
52+
%val4_tmp = call i64 @llvm.bswap.i64(i64 %val3_tmp)
53+
store volatile i64 %val4_tmp, i64* @var64
54+
ret void
4255
}
4356

4457
define void @rev16_i32() {
4558
; CHECK-LABEL: rev16_i32:
46-
%val0_tmp = load i32, i32* @var32
47-
%val1_tmp = shl i32 %val0_tmp, 16
48-
%val2_tmp = lshr i32 %val0_tmp, 16
49-
%val3_tmp = or i32 %val1_tmp, %val2_tmp
50-
%val4_tmp = call i32 @llvm.bswap.i32(i32 %val3_tmp)
51-
; CHECK: rev16 {{w[0-9]+}}, {{w[0-9]+}}
52-
store volatile i32 %val4_tmp, i32* @var32
53-
ret void
59+
; CHECK: // %bb.0:
60+
; CHECK-NEXT: adrp x8, :got:var32
61+
; CHECK-NEXT: ldr x8, [x8, :got_lo12:var32]
62+
; CHECK-NEXT: ldr w9, [x8]
63+
; CHECK-NEXT: rev16 w9, w9
64+
; CHECK-NEXT: str w9, [x8]
65+
; CHECK-NEXT: ret
66+
%val0_tmp = load i32, i32* @var32
67+
%val1_tmp = shl i32 %val0_tmp, 16
68+
%val2_tmp = lshr i32 %val0_tmp, 16
69+
%val3_tmp = or i32 %val1_tmp, %val2_tmp
70+
%val4_tmp = call i32 @llvm.bswap.i32(i32 %val3_tmp)
71+
store volatile i32 %val4_tmp, i32* @var32
72+
ret void
5473
}
5574

5675
define void @clz_zerodef_i32() {
5776
; CHECK-LABEL: clz_zerodef_i32:
58-
%val0_tmp = load i32, i32* @var32
59-
%val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 0)
60-
; CHECK: clz {{w[0-9]+}}, {{w[0-9]+}}
61-
store volatile i32 %val4_tmp, i32* @var32
62-
ret void
77+
; CHECK: // %bb.0:
78+
; CHECK-NEXT: adrp x8, :got:var32
79+
; CHECK-NEXT: ldr x8, [x8, :got_lo12:var32]
80+
; CHECK-NEXT: ldr w9, [x8]
81+
; CHECK-NEXT: clz w9, w9
82+
; CHECK-NEXT: str w9, [x8]
83+
; CHECK-NEXT: ret
84+
%val0_tmp = load i32, i32* @var32
85+
%val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 0)
86+
store volatile i32 %val4_tmp, i32* @var32
87+
ret void
6388
}
6489

6590
define void @clz_zerodef_i64() {
6691
; CHECK-LABEL: clz_zerodef_i64:
67-
%val0_tmp = load i64, i64* @var64
68-
%val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 0)
69-
; CHECK: clz {{x[0-9]+}}, {{x[0-9]+}}
70-
store volatile i64 %val4_tmp, i64* @var64
71-
ret void
92+
; CHECK: // %bb.0:
93+
; CHECK-NEXT: adrp x8, :got:var64
94+
; CHECK-NEXT: ldr x8, [x8, :got_lo12:var64]
95+
; CHECK-NEXT: ldr x9, [x8]
96+
; CHECK-NEXT: clz x9, x9
97+
; CHECK-NEXT: str x9, [x8]
98+
; CHECK-NEXT: ret
99+
%val0_tmp = load i64, i64* @var64
100+
%val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 0)
101+
store volatile i64 %val4_tmp, i64* @var64
102+
ret void
72103
}
73104

74105
define void @clz_zeroundef_i32() {
75106
; CHECK-LABEL: clz_zeroundef_i32:
76-
%val0_tmp = load i32, i32* @var32
77-
%val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 1)
78-
; CHECK: clz {{w[0-9]+}}, {{w[0-9]+}}
79-
store volatile i32 %val4_tmp, i32* @var32
80-
ret void
107+
; CHECK: // %bb.0:
108+
; CHECK-NEXT: adrp x8, :got:var32
109+
; CHECK-NEXT: ldr x8, [x8, :got_lo12:var32]
110+
; CHECK-NEXT: ldr w9, [x8]
111+
; CHECK-NEXT: clz w9, w9
112+
; CHECK-NEXT: str w9, [x8]
113+
; CHECK-NEXT: ret
114+
%val0_tmp = load i32, i32* @var32
115+
%val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 1)
116+
store volatile i32 %val4_tmp, i32* @var32
117+
ret void
81118
}
82119

83120
define void @clz_zeroundef_i64() {
84121
; CHECK-LABEL: clz_zeroundef_i64:
85-
%val0_tmp = load i64, i64* @var64
86-
%val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 1)
87-
; CHECK: clz {{x[0-9]+}}, {{x[0-9]+}}
88-
store volatile i64 %val4_tmp, i64* @var64
89-
ret void
122+
; CHECK: // %bb.0:
123+
; CHECK-NEXT: adrp x8, :got:var64
124+
; CHECK-NEXT: ldr x8, [x8, :got_lo12:var64]
125+
; CHECK-NEXT: ldr x9, [x8]
126+
; CHECK-NEXT: clz x9, x9
127+
; CHECK-NEXT: str x9, [x8]
128+
; CHECK-NEXT: ret
129+
%val0_tmp = load i64, i64* @var64
130+
%val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 1)
131+
store volatile i64 %val4_tmp, i64* @var64
132+
ret void
90133
}
91134

92135
define void @cttz_zerodef_i32() {
93136
; CHECK-LABEL: cttz_zerodef_i32:
94-
%val0_tmp = load i32, i32* @var32
95-
%val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 0)
96-
; CHECK: rbit [[REVERSED:w[0-9]+]], {{w[0-9]+}}
97-
; CHECK: clz {{w[0-9]+}}, [[REVERSED]]
98-
store volatile i32 %val4_tmp, i32* @var32
99-
ret void
137+
; CHECK: // %bb.0:
138+
; CHECK-NEXT: adrp x8, :got:var32
139+
; CHECK-NEXT: ldr x8, [x8, :got_lo12:var32]
140+
; CHECK-NEXT: ldr w9, [x8]
141+
; CHECK-NEXT: rbit w9, w9
142+
; CHECK-NEXT: clz w9, w9
143+
; CHECK-NEXT: str w9, [x8]
144+
; CHECK-NEXT: ret
145+
%val0_tmp = load i32, i32* @var32
146+
%val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 0)
147+
store volatile i32 %val4_tmp, i32* @var32
148+
ret void
100149
}
101150

102151
define void @cttz_zerodef_i64() {
103152
; CHECK-LABEL: cttz_zerodef_i64:
104-
%val0_tmp = load i64, i64* @var64
105-
%val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 0)
106-
; CHECK: rbit [[REVERSED:x[0-9]+]], {{x[0-9]+}}
107-
; CHECK: clz {{x[0-9]+}}, [[REVERSED]]
108-
store volatile i64 %val4_tmp, i64* @var64
109-
ret void
153+
; CHECK: // %bb.0:
154+
; CHECK-NEXT: adrp x8, :got:var64
155+
; CHECK-NEXT: ldr x8, [x8, :got_lo12:var64]
156+
; CHECK-NEXT: ldr x9, [x8]
157+
; CHECK-NEXT: rbit x9, x9
158+
; CHECK-NEXT: clz x9, x9
159+
; CHECK-NEXT: str x9, [x8]
160+
; CHECK-NEXT: ret
161+
%val0_tmp = load i64, i64* @var64
162+
%val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 0)
163+
store volatile i64 %val4_tmp, i64* @var64
164+
ret void
110165
}
111166

112167
define void @cttz_zeroundef_i32() {
113168
; CHECK-LABEL: cttz_zeroundef_i32:
114-
%val0_tmp = load i32, i32* @var32
115-
%val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 1)
116-
; CHECK: rbit [[REVERSED:w[0-9]+]], {{w[0-9]+}}
117-
; CHECK: clz {{w[0-9]+}}, [[REVERSED]]
118-
store volatile i32 %val4_tmp, i32* @var32
119-
ret void
169+
; CHECK: // %bb.0:
170+
; CHECK-NEXT: adrp x8, :got:var32
171+
; CHECK-NEXT: ldr x8, [x8, :got_lo12:var32]
172+
; CHECK-NEXT: ldr w9, [x8]
173+
; CHECK-NEXT: rbit w9, w9
174+
; CHECK-NEXT: clz w9, w9
175+
; CHECK-NEXT: str w9, [x8]
176+
; CHECK-NEXT: ret
177+
%val0_tmp = load i32, i32* @var32
178+
%val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 1)
179+
store volatile i32 %val4_tmp, i32* @var32
180+
ret void
120181
}
121182

122183
define void @cttz_zeroundef_i64() {
123184
; CHECK-LABEL: cttz_zeroundef_i64:
124-
%val0_tmp = load i64, i64* @var64
125-
%val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 1)
126-
; CHECK: rbit [[REVERSED:x[0-9]+]], {{x[0-9]+}}
127-
; CHECK: clz {{x[0-9]+}}, [[REVERSED]]
128-
store volatile i64 %val4_tmp, i64* @var64
129-
ret void
185+
; CHECK: // %bb.0:
186+
; CHECK-NEXT: adrp x8, :got:var64
187+
; CHECK-NEXT: ldr x8, [x8, :got_lo12:var64]
188+
; CHECK-NEXT: ldr x9, [x8]
189+
; CHECK-NEXT: rbit x9, x9
190+
; CHECK-NEXT: clz x9, x9
191+
; CHECK-NEXT: str x9, [x8]
192+
; CHECK-NEXT: ret
193+
%val0_tmp = load i64, i64* @var64
194+
%val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 1)
195+
store volatile i64 %val4_tmp, i64* @var64
196+
ret void
130197
}
131198

132-
; These two are just compilation tests really: the operation's set to Expand in
133-
; ISelLowering.
134199
define void @ctpop_i32() {
135-
; CHECK-LABEL: ctpop_i32:
136-
%val0_tmp = load i32, i32* @var32
137-
%val4_tmp = call i32 @llvm.ctpop.i32(i32 %val0_tmp)
138-
store volatile i32 %val4_tmp, i32* @var32
139-
ret void
200+
; CHECK-SDAG-LABEL: ctpop_i32:
201+
; CHECK-SDAG: // %bb.0:
202+
; CHECK-SDAG-NEXT: adrp x8, :got:var32
203+
; CHECK-SDAG-NEXT: ldr x8, [x8, :got_lo12:var32]
204+
; CHECK-SDAG-NEXT: ldr w9, [x8]
205+
; CHECK-SDAG-NEXT: fmov d0, x9
206+
; CHECK-SDAG-NEXT: cnt v0.8b, v0.8b
207+
; CHECK-SDAG-NEXT: uaddlv h0, v0.8b
208+
; CHECK-SDAG-NEXT: fmov w9, s0
209+
; CHECK-SDAG-NEXT: str w9, [x8]
210+
; CHECK-SDAG-NEXT: ret
211+
;
212+
; CHECK-GISEL-LABEL: ctpop_i32:
213+
; CHECK-GISEL: // %bb.0:
214+
; CHECK-GISEL-NEXT: adrp x8, :got:var32
215+
; CHECK-GISEL-NEXT: ldr x8, [x8, :got_lo12:var32]
216+
; CHECK-GISEL-NEXT: ldr w9, [x8]
217+
; CHECK-GISEL-NEXT: fmov d0, x9
218+
; CHECK-GISEL-NEXT: cnt v0.8b, v0.8b
219+
; CHECK-GISEL-NEXT: uaddlv h0, v0.8b
220+
; CHECK-GISEL-NEXT: str s0, [x8]
221+
; CHECK-GISEL-NEXT: ret
222+
%val0_tmp = load i32, i32* @var32
223+
%val4_tmp = call i32 @llvm.ctpop.i32(i32 %val0_tmp)
224+
store volatile i32 %val4_tmp, i32* @var32
225+
ret void
140226
}
141227

142228
define void @ctpop_i64() {
143-
; CHECK-LABEL: ctpop_i64:
144-
%val0_tmp = load i64, i64* @var64
145-
%val4_tmp = call i64 @llvm.ctpop.i64(i64 %val0_tmp)
146-
store volatile i64 %val4_tmp, i64* @var64
147-
ret void
229+
; CHECK-SDAG-LABEL: ctpop_i64:
230+
; CHECK-SDAG: // %bb.0:
231+
; CHECK-SDAG-NEXT: adrp x8, :got:var64
232+
; CHECK-SDAG-NEXT: ldr x8, [x8, :got_lo12:var64]
233+
; CHECK-SDAG-NEXT: ldr d0, [x8]
234+
; CHECK-SDAG-NEXT: cnt v0.8b, v0.8b
235+
; CHECK-SDAG-NEXT: uaddlv h0, v0.8b
236+
; CHECK-SDAG-NEXT: fmov w9, s0
237+
; CHECK-SDAG-NEXT: str x9, [x8]
238+
; CHECK-SDAG-NEXT: ret
239+
;
240+
; CHECK-GISEL-LABEL: ctpop_i64:
241+
; CHECK-GISEL: // %bb.0:
242+
; CHECK-GISEL-NEXT: adrp x8, :got:var64
243+
; CHECK-GISEL-NEXT: ldr x8, [x8, :got_lo12:var64]
244+
; CHECK-GISEL-NEXT: ldr x9, [x8]
245+
; CHECK-GISEL-NEXT: fmov d0, x9
246+
; CHECK-GISEL-NEXT: cnt v0.8b, v0.8b
247+
; CHECK-GISEL-NEXT: uaddlv h0, v0.8b
248+
; CHECK-GISEL-NEXT: fmov w9, s0
249+
; CHECK-GISEL-NEXT: mov w9, w9
250+
; CHECK-GISEL-NEXT: str x9, [x8]
251+
; CHECK-GISEL-NEXT: ret
252+
%val0_tmp = load i64, i64* @var64
253+
%val4_tmp = call i64 @llvm.ctpop.i64(i64 %val0_tmp)
254+
store volatile i64 %val4_tmp, i64* @var64
255+
ret void
148256
}
149257

150258

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