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[RISCV] Rename XTHead DecoderNamespaces to match their extension names include the 'X'. NFC
This is consistent with other vendor extensions.
1 parent 0c7d897 commit b4bb111

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2 files changed

+29
-29
lines changed

2 files changed

+29
-29
lines changed

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -529,32 +529,32 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
529529
"RVZfinx table (Float in Integer)");
530530
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXVentanaCondOps,
531531
DecoderTableVentana32, "Ventana custom opcode table");
532-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBa, DecoderTableTHeadBa32,
532+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBa, DecoderTableXTHeadBa32,
533533
"XTHeadBa custom opcode table");
534-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBb, DecoderTableTHeadBb32,
534+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBb, DecoderTableXTHeadBb32,
535535
"XTHeadBb custom opcode table");
536-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBs, DecoderTableTHeadBs32,
536+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBs, DecoderTableXTHeadBs32,
537537
"XTHeadBs custom opcode table");
538538
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadCondMov,
539-
DecoderTableTHeadCondMov32,
539+
DecoderTableXTHeadCondMov32,
540540
"XTHeadCondMov custom opcode table");
541-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadCmo, DecoderTableTHeadCmo32,
541+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadCmo, DecoderTableXTHeadCmo32,
542542
"XTHeadCmo custom opcode table");
543543
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadFMemIdx,
544-
DecoderTableTHeadFMemIdx32,
544+
DecoderTableXTHeadFMemIdx32,
545545
"XTHeadFMemIdx custom opcode table");
546-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMac, DecoderTableTHeadMac32,
546+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMac, DecoderTableXTHeadMac32,
547547
"XTHeadMac custom opcode table");
548548
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMemIdx,
549-
DecoderTableTHeadMemIdx32,
549+
DecoderTableXTHeadMemIdx32,
550550
"XTHeadMemIdx custom opcode table");
551551
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMemPair,
552-
DecoderTableTHeadMemPair32,
552+
DecoderTableXTHeadMemPair32,
553553
"XTHeadMemPair custom opcode table");
554554
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadSync,
555-
DecoderTableTHeadSync32,
555+
DecoderTableXTHeadSync32,
556556
"XTHeadSync custom opcode table");
557-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadVdot, DecoderTableTHeadV32,
557+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadVdot, DecoderTableXTHeadVdot32,
558558
"XTHeadVdot custom opcode table");
559559
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32,
560560
"SiFive VCIX custom opcode table");

llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -38,15 +38,15 @@ class THInstVdotVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
3838
: RVInstVV<funct6, opv, outs, ins, opcodestr, argstr> {
3939
let Inst{26} = 0;
4040
let Inst{6-0} = OPC_CUSTOM_0.Value;
41-
let DecoderNamespace = "THeadV";
41+
let DecoderNamespace = "XTHeadVdot";
4242
}
4343

4444
class THInstVdotVX<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
4545
string opcodestr, string argstr>
4646
: RVInstVX<funct6, opv, outs, ins, opcodestr, argstr> {
4747
let Inst{26} = 1;
4848
let Inst{6-0} = OPC_CUSTOM_0.Value;
49-
let DecoderNamespace = "THeadV";
49+
let DecoderNamespace = "XTHeadVdot";
5050
}
5151

5252
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
@@ -63,7 +63,7 @@ class THVdotALUrVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
6363
opcodestr, "$vd, $rs1, $vs2$vm">;
6464
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
6565

66-
let Predicates = [HasVendorXTHeadBa], DecoderNamespace = "THeadBa",
66+
let Predicates = [HasVendorXTHeadBa], DecoderNamespace = "XTHeadBa",
6767
hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
6868
class THShiftALU_rri<bits<3> funct3, string opcodestr>
6969
: RVInstR<0, funct3, OPC_CUSTOM_0, (outs GPR:$rd),
@@ -74,7 +74,7 @@ class THShiftALU_rri<bits<3> funct3, string opcodestr>
7474
let Inst{26-25} = uimm2;
7575
}
7676

77-
let Predicates = [HasVendorXTHeadBb], DecoderNamespace = "THeadBb",
77+
let Predicates = [HasVendorXTHeadBb], DecoderNamespace = "XTHeadBb",
7878
hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
7979
class THShift_ri<bits<5> funct5, bits<3> funct3, string opcodestr>
8080
: RVInstIShift<funct5, funct3, OPC_CUSTOM_0, (outs GPR:$rd),
@@ -96,14 +96,14 @@ class THRev_r<bits<5> funct5, bits<2> funct2, string opcodestr>
9696
(outs GPR:$rd), (ins GPR:$rs1), opcodestr, "$rd, $rs1">;
9797
}
9898

99-
let Predicates = [HasVendorXTHeadBb, IsRV64], DecoderNamespace = "THeadBb",
99+
let Predicates = [HasVendorXTHeadBb, IsRV64], DecoderNamespace = "XTHeadBb",
100100
hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
101101
class THShiftW_ri<bits<7> funct7, bits<3> funct3, string opcodestr>
102102
: RVInstIShiftW<funct7, funct3, OPC_CUSTOM_0, (outs GPR:$rd),
103103
(ins GPR:$rs1, uimm5:$shamt),
104104
opcodestr, "$rd, $rs1, $shamt">;
105105

106-
let Predicates = [HasVendorXTHeadCondMov], DecoderNamespace = "THeadCondMov",
106+
let Predicates = [HasVendorXTHeadCondMov], DecoderNamespace = "XTHeadCondMov",
107107
hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in
108108
class THCondMov_rr<bits<7> funct7, string opcodestr>
109109
: RVInstR<funct7, 0b001, OPC_CUSTOM_0, (outs GPR:$rd_wb),
@@ -112,7 +112,7 @@ class THCondMov_rr<bits<7> funct7, string opcodestr>
112112
let Constraints = "$rd_wb = $rd";
113113
}
114114

115-
let Predicates = [HasVendorXTHeadMac], DecoderNamespace = "THeadMac",
115+
let Predicates = [HasVendorXTHeadMac], DecoderNamespace = "XTHeadMac",
116116
hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in
117117
class THMulAccumulate_rr<bits<7> funct7, string opcodestr>
118118
: RVInstR<funct7, 0b001, OPC_CUSTOM_0, (outs GPR:$rd_wb),
@@ -121,7 +121,7 @@ class THMulAccumulate_rr<bits<7> funct7, string opcodestr>
121121
let Constraints = "$rd_wb = $rd";
122122
}
123123

124-
let Predicates = [HasVendorXTHeadMemPair], DecoderNamespace = "THeadMemPair",
124+
let Predicates = [HasVendorXTHeadMemPair], DecoderNamespace = "XTHeadMemPair",
125125
hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
126126
class THLoadPair<bits<5> funct5, string opcodestr>
127127
: RVInstR<!shl(funct5, 2), 0b100, OPC_CUSTOM_0,
@@ -134,7 +134,7 @@ class THLoadPair<bits<5> funct5, string opcodestr>
134134
let Constraints = "@earlyclobber $rd,@earlyclobber $rs2";
135135
}
136136

137-
let Predicates = [HasVendorXTHeadMemPair], DecoderNamespace = "THeadMemPair",
137+
let Predicates = [HasVendorXTHeadMemPair], DecoderNamespace = "XTHeadMemPair",
138138
hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
139139
class THStorePair<bits<5> funct5, string opcodestr>
140140
: RVInstR<!shl(funct5, 2), 0b101, OPC_CUSTOM_0,
@@ -249,7 +249,7 @@ def TH_SRRIW : THShiftW_ri<0b0001010, 0b001, "th.srriw">;
249249
def TH_REVW : THRev_r<0b10010, 0b00, "th.revw">;
250250
} // Predicates = [HasVendorXTHeadBb, IsRV64]
251251

252-
let Predicates = [HasVendorXTHeadBs], DecoderNamespace = "THeadBs" in {
252+
let Predicates = [HasVendorXTHeadBs], DecoderNamespace = "XTHeadBs" in {
253253
let IsSignExtendingOpW = 1 in
254254
def TH_TST : RVBShift_ri<0b10001, 0b001, OPC_CUSTOM_0, "th.tst">,
255255
Sched<[WriteSingleBitImm, ReadSingleBitImm]>;
@@ -292,7 +292,7 @@ def TH_SDD : THStorePair<0b11111, "th.sdd">,
292292
Sched<[WriteSTD, WriteSTD, ReadStoreData, ReadMemBase]>;
293293
}
294294

295-
let Predicates = [HasVendorXTHeadMemIdx], DecoderNamespace = "THeadMemIdx" in {
295+
let Predicates = [HasVendorXTHeadMemIdx], DecoderNamespace = "XTHeadMemIdx" in {
296296
// T-Head Load/Store + Update instructions.
297297
def TH_LBIA : THLoadUpdate<0b00011, "th.lbia">,
298298
Sched<[WriteLDB, ReadMemBase]>;
@@ -372,7 +372,7 @@ def TH_SURW : THStoreIndexed<GPR, 0b01010, "th.surw">,
372372
Sched<[WriteLDB, ReadMemBase]>;
373373
}
374374

375-
let Predicates = [HasVendorXTHeadMemIdx, IsRV64], DecoderNamespace = "THeadMemIdx" in {
375+
let Predicates = [HasVendorXTHeadMemIdx, IsRV64], DecoderNamespace = "XTHeadMemIdx" in {
376376
// T-Head Load/Store + Update instructions.
377377
def TH_LWUIA : THLoadUpdate<0b11011, "th.lwuia">,
378378
Sched<[WriteLDH, ReadMemBase]>;
@@ -409,31 +409,31 @@ def TH_SURD : THStoreIndexed<GPR, 0b01110, "th.surd">,
409409
// T-Head Load/Store Indexed instructions for floating point registers.
410410

411411
let Predicates = [HasVendorXTHeadFMemIdx, HasStdExtF],
412-
DecoderNamespace = "THeadFMemIdx" in {
412+
DecoderNamespace = "XTHeadFMemIdx" in {
413413
def TH_FLRW : THLoadIndexed<FPR32, 0b01000, "th.flrw">,
414414
Sched<[WriteFLD32, ReadFMemBase]>;
415415
def TH_FSRW : THStoreIndexed<FPR32, 0b01000, "th.fsrw">,
416416
Sched<[WriteFST32, ReadFStoreData, ReadFMemBase]>;
417417
}
418418

419419
let Predicates = [HasVendorXTHeadFMemIdx, HasStdExtD],
420-
DecoderNamespace = "THeadFMemIdx" in {
420+
DecoderNamespace = "XTHeadFMemIdx" in {
421421
def TH_FLRD : THLoadIndexed<FPR64, 0b01100, "th.flrd">,
422422
Sched<[WriteFLD64, ReadFMemBase]>;
423423
def TH_FSRD : THStoreIndexed<FPR64, 0b01100, "th.fsrd">,
424424
Sched<[WriteFST64, ReadFStoreData, ReadFMemBase]>;
425425
}
426426

427427
let Predicates = [HasVendorXTHeadFMemIdx, HasStdExtF, IsRV64],
428-
DecoderNamespace = "THeadFMemIdx" in {
428+
DecoderNamespace = "XTHeadFMemIdx" in {
429429
def TH_FLURW : THLoadIndexed<FPR32, 0b01010, "th.flurw">,
430430
Sched<[WriteFLD32, ReadFMemBase]>;
431431
def TH_FSURW : THStoreIndexed<FPR32, 0b01010, "th.fsurw">,
432432
Sched<[WriteFST32, ReadFStoreData, ReadFMemBase]>;
433433
}
434434

435435
let Predicates = [HasVendorXTHeadFMemIdx, HasStdExtD, IsRV64],
436-
DecoderNamespace = "THeadFMemIdx" in {
436+
DecoderNamespace = "XTHeadFMemIdx" in {
437437
def TH_FLURD : THLoadIndexed<FPR64, 0b01110, "th.flurd">,
438438
Sched<[WriteFLD64, ReadFMemBase]>;
439439
def TH_FSURD : THStoreIndexed<FPR64, 0b01110, "th.fsurd">,
@@ -724,7 +724,7 @@ let Predicates = [HasVendorXTHeadMemPair] in {
724724
(TH_SWD GPR:$rd1, GPR:$rd2, GPR:$rs1, uimm2_3:$uimm2_3, 3)>;
725725
}
726726

727-
let Predicates = [HasVendorXTHeadCmo], DecoderNamespace = "THeadCmo" in {
727+
let Predicates = [HasVendorXTHeadCmo], DecoderNamespace = "XTHeadCmo" in {
728728
def TH_DCACHE_CSW : THCacheInst_r<0b00001, "th.dcache.csw">;
729729
def TH_DCACHE_ISW : THCacheInst_r<0b00010, "th.dcache.isw">;
730730
def TH_DCACHE_CISW : THCacheInst_r<0b00011, "th.dcache.cisw">;
@@ -749,7 +749,7 @@ def TH_L2CACHE_IALL : THCacheInst_void<0b10110, "th.l2cache.iall">;
749749
def TH_L2CACHE_CIALL : THCacheInst_void<0b10111, "th.l2cache.ciall">;
750750
}
751751

752-
let Predicates = [HasVendorXTHeadSync], DecoderNamespace = "THeadSync" in {
752+
let Predicates = [HasVendorXTHeadSync], DecoderNamespace = "XTHeadSync" in {
753753
def TH_SFENCE_VMAS : THCacheInst_rr<0b0000010, "th.sfence.vmas">;
754754
def TH_SYNC : THCacheInst_void<0b11000, "th.sync">;
755755
def TH_SYNC_S : THCacheInst_void<0b11001, "th.sync.s">;

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