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[X86] Add SM3 instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D155147
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‎clang/docs/ReleaseNotes.rst

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@@ -817,6 +817,10 @@ X86 Support
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* Support intrinsic of ``_mm256_sha512msg1_epi64``.
818818
* Support intrinsic of ``_mm256_sha512msg2_epi64``.
819819
* Support intrinsic of ``_mm256_sha512rnds2_epi64``.
820+
- Support ISA of ``SM3``.
821+
* Support intrinsic of ``_mm_sm3msg1_epi32``.
822+
* Support intrinsic of ``_mm_sm3msg2_epi32``.
823+
* Support intrinsic of ``_mm_sm3rnds2_epi32``.
820824

821825
Arm and AArch64 Support
822826
^^^^^^^^^^^^^^^^^^^^^^^

‎clang/include/clang/Basic/BuiltinsX86.def

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@@ -2146,6 +2146,11 @@ TARGET_HEADER_BUILTIN(_InterlockedIncrement64, "WiWiD*", "nh", INTRIN_H, ALL
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TARGET_HEADER_BUILTIN(_InterlockedOr64, "WiWiD*Wi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
21472147
TARGET_HEADER_BUILTIN(_InterlockedXor64, "WiWiD*Wi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
21482148

2149+
// SM3
2150+
TARGET_BUILTIN(__builtin_ia32_vsm3msg1, "V4UiV4UiV4UiV4Ui", "nV:128:", "sm3")
2151+
TARGET_BUILTIN(__builtin_ia32_vsm3msg2, "V4UiV4UiV4UiV4Ui", "nV:128:", "sm3")
2152+
TARGET_BUILTIN(__builtin_ia32_vsm3rnds2, "V4UiV4UiV4UiV4UiIUi", "nV:128:", "sm3")
2153+
21492154
#undef BUILTIN
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#undef TARGET_BUILTIN
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#undef TARGET_HEADER_BUILTIN

‎clang/include/clang/Driver/Options.td

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@@ -5058,6 +5058,8 @@ def msha : Flag<["-"], "msha">, Group<m_x86_Features_Group>;
50585058
def mno_sha : Flag<["-"], "mno-sha">, Group<m_x86_Features_Group>;
50595059
def msha512 : Flag<["-"], "msha512">, Group<m_x86_Features_Group>;
50605060
def mno_sha512 : Flag<["-"], "mno-sha512">, Group<m_x86_Features_Group>;
5061+
def msm3 : Flag<["-"], "msm3">, Group<m_x86_Features_Group>;
5062+
def mno_sm3 : Flag<["-"], "mno-sm3">, Group<m_x86_Features_Group>;
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def mtbm : Flag<["-"], "mtbm">, Group<m_x86_Features_Group>;
50625064
def mno_tbm : Flag<["-"], "mno-tbm">, Group<m_x86_Features_Group>;
50635065
def mtsxldtrk : Flag<["-"], "mtsxldtrk">, Group<m_x86_Features_Group>;

‎clang/lib/Basic/Targets/X86.cpp

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Original file line numberDiff line numberDiff line change
@@ -265,6 +265,8 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
265265
HasSHA512 = true;
266266
} else if (Feature == "+shstk") {
267267
HasSHSTK = true;
268+
} else if (Feature == "+sm3") {
269+
HasSM3 = true;
268270
} else if (Feature == "+movbe") {
269271
HasMOVBE = true;
270272
} else if (Feature == "+sgx") {
@@ -776,6 +778,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
776778
Builder.defineMacro("__SHSTK__");
777779
if (HasSGX)
778780
Builder.defineMacro("__SGX__");
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if (HasSM3)
782+
Builder.defineMacro("__SM3__");
779783
if (HasPREFETCHI)
780784
Builder.defineMacro("__PREFETCHI__");
781785
if (HasPREFETCHWT1)
@@ -1005,6 +1009,7 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
10051009
.Case("sha", true)
10061010
.Case("sha512", true)
10071011
.Case("shstk", true)
1012+
.Case("sm3", true)
10081013
.Case("sse", true)
10091014
.Case("sse2", true)
10101015
.Case("sse3", true)
@@ -1111,6 +1116,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
11111116
.Case("sha", HasSHA)
11121117
.Case("sha512", HasSHA512)
11131118
.Case("shstk", HasSHSTK)
1119+
.Case("sm3", HasSM3)
11141120
.Case("sse", SSELevel >= SSE1)
11151121
.Case("sse2", SSELevel >= SSE2)
11161122
.Case("sse3", SSELevel >= SSE3)

‎clang/lib/Basic/Targets/X86.h

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@@ -114,6 +114,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
114114
bool HasSHA = false;
115115
bool HasSHA512 = false;
116116
bool HasSHSTK = false;
117+
bool HasSM3 = false;
117118
bool HasSGX = false;
118119
bool HasCX8 = false;
119120
bool HasCX16 = false;

‎clang/lib/Headers/CMakeLists.txt

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@@ -205,6 +205,7 @@ set(x86_files
205205
sgxintrin.h
206206
sha512intrin.h
207207
shaintrin.h
208+
sm3intrin.h
208209
smmintrin.h
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tbmintrin.h
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tmmintrin.h

‎clang/lib/Headers/immintrin.h

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@@ -274,6 +274,11 @@
274274
#include <sha512intrin.h>
275275
#endif
276276

277+
#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) || \
278+
defined(__SM3__)
279+
#include <sm3intrin.h>
280+
#endif
281+
277282
#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) || \
278283
defined(__RDPID__)
279284
/// Returns the value of the IA32_TSC_AUX MSR (0xc0000103).

‎clang/lib/Headers/sm3intrin.h

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@@ -0,0 +1,238 @@
1+
/*===-------------------- sm3intrin.h - SM3 intrinsics ---------------------===
2+
*
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* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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* See https://llvm.org/LICENSE.txt for license information.
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* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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*
7+
*===-----------------------------------------------------------------------===
8+
*/
9+
10+
#ifndef __IMMINTRIN_H
11+
#error "Never use <sm3intrin.h> directly; include <immintrin.h> instead."
12+
#endif // __IMMINTRIN_H
13+
14+
#ifndef __SM3INTRIN_H
15+
#define __SM3INTRIN_H
16+
17+
#define __DEFAULT_FN_ATTRS128 \
18+
__attribute__((__always_inline__, __nodebug__, __target__("sm3"), \
19+
__min_vector_width__(128)))
20+
21+
/// This intrinisc is one of the two SM3 message scheduling intrinsics. The
22+
/// intrinsic performs an initial calculation for the next four SM3 message
23+
/// words. The calculated results are stored in \a dst.
24+
///
25+
/// \headerfile <immintrin.h>
26+
///
27+
/// \code
28+
/// __m128i _mm_sm3msg1_epi32(__m128i __A, __m128i __B, __m128i __C)
29+
/// \endcode
30+
///
31+
/// This intrinsic corresponds to the \c VSM3MSG1 instruction.
32+
///
33+
/// \param __A
34+
/// A 128-bit vector of [4 x int].
35+
/// \param __B
36+
/// A 128-bit vector of [4 x int].
37+
/// \param __C
38+
/// A 128-bit vector of [4 x int].
39+
/// \returns
40+
/// A 128-bit vector of [4 x int].
41+
///
42+
/// \code{.operation}
43+
/// DEFINE ROL32(dword, n) {
44+
/// count := n % 32
45+
/// dest := (dword << count) | (dword >> (32 - count))
46+
/// RETURN dest
47+
/// }
48+
/// DEFINE P1(x) {
49+
/// RETURN x ^ ROL32(x, 15) ^ ROL32(x, 23)
50+
/// }
51+
/// W[0] := __C.dword[0]
52+
/// W[1] := __C.dword[1]
53+
/// W[2] := __C.dword[2]
54+
/// W[3] := __C.dword[3]
55+
/// W[7] := __A.dword[0]
56+
/// W[8] := __A.dword[1]
57+
/// W[9] := __A.dword[2]
58+
/// W[10] := __A.dword[3]
59+
/// W[13] := __B.dword[0]
60+
/// W[14] := __B.dword[1]
61+
/// W[15] := __B.dword[2]
62+
/// TMP0 := W[7] ^ W[0] ^ ROL32(W[13], 15)
63+
/// TMP1 := W[8] ^ W[1] ^ ROL32(W[14], 15)
64+
/// TMP2 := W[9] ^ W[2] ^ ROL32(W[15], 15)
65+
/// TMP3 := W[10] ^ W[3]
66+
/// dst.dword[0] := P1(TMP0)
67+
/// dst.dword[1] := P1(TMP1)
68+
/// dst.dword[2] := P1(TMP2)
69+
/// dst.dword[3] := P1(TMP3)
70+
/// dst[MAX:128] := 0
71+
/// \endcode
72+
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_sm3msg1_epi32(__m128i __A,
73+
__m128i __B,
74+
__m128i __C) {
75+
return (__m128i)__builtin_ia32_vsm3msg1((__v4su)__A, (__v4su)__B,
76+
(__v4su)__C);
77+
}
78+
79+
/// This intrinisc is one of the two SM3 message scheduling intrinsics. The
80+
/// intrinsic performs the final calculation for the next four SM3 message
81+
/// words. The calculated results are stored in \a dst.
82+
///
83+
/// \headerfile <immintrin.h>
84+
///
85+
/// \code
86+
/// __m128i _mm_sm3msg2_epi32(__m128i __A, __m128i __B, __m128i __C)
87+
/// \endcode
88+
///
89+
/// This intrinsic corresponds to the \c VSM3MSG2 instruction.
90+
///
91+
/// \param __A
92+
/// A 128-bit vector of [4 x int].
93+
/// \param __B
94+
/// A 128-bit vector of [4 x int].
95+
/// \param __C
96+
/// A 128-bit vector of [4 x int].
97+
/// \returns
98+
/// A 128-bit vector of [4 x int].
99+
///
100+
/// \code{.operation}
101+
/// DEFINE ROL32(dword, n) {
102+
/// count := n % 32
103+
/// dest := (dword << count) | (dword >> (32-count))
104+
/// RETURN dest
105+
/// }
106+
/// WTMP[0] := __A.dword[0]
107+
/// WTMP[1] := __A.dword[1]
108+
/// WTMP[2] := __A.dword[2]
109+
/// WTMP[3] := __A.dword[3]
110+
/// W[3] := __B.dword[0]
111+
/// W[4] := __B.dword[1]
112+
/// W[5] := __B.dword[2]
113+
/// W[6] := __B.dword[3]
114+
/// W[10] := __C.dword[0]
115+
/// W[11] := __C.dword[1]
116+
/// W[12] := __C.dword[2]
117+
/// W[13] := __C.dword[3]
118+
/// W[16] := ROL32(W[3], 7) ^ W[10] ^ WTMP[0]
119+
/// W[17] := ROL32(W[4], 7) ^ W[11] ^ WTMP[1]
120+
/// W[18] := ROL32(W[5], 7) ^ W[12] ^ WTMP[2]
121+
/// W[19] := ROL32(W[6], 7) ^ W[13] ^ WTMP[3]
122+
/// W[19] := W[19] ^ ROL32(W[16], 6) ^ ROL32(W[16], 15) ^ ROL32(W[16], 30)
123+
/// dst.dword[0] := W[16]
124+
/// dst.dword[1] := W[17]
125+
/// dst.dword[2] := W[18]
126+
/// dst.dword[3] := W[19]
127+
/// dst[MAX:128] := 0
128+
/// \endcode
129+
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_sm3msg2_epi32(__m128i __A,
130+
__m128i __B,
131+
__m128i __C) {
132+
return (__m128i)__builtin_ia32_vsm3msg2((__v4su)__A, (__v4su)__B,
133+
(__v4su)__C);
134+
}
135+
136+
/// This intrinsic performs two rounds of SM3 operation using initial SM3 state
137+
/// (C, D, G, H) from \a __A, an initial SM3 states (A, B, E, F)
138+
/// from \a __B and a pre-computed words from the \a __C. \a __A with
139+
/// initial SM3 state of (C, D, G, H) assumes input of non-rotated left
140+
/// variables from previous state. The updated SM3 state (A, B, E, F) is
141+
/// written to \a __A. The \a imm8 should contain the even round number
142+
/// for the first of the two rounds computed by this instruction. The
143+
/// computation masks the \a imm8 value by AND’ing it with 0x3E so that only
144+
/// even round numbers from 0 through 62 are used for this operation. The
145+
/// calculated results are stored in \a dst.
146+
///
147+
/// \headerfile <immintrin.h>
148+
///
149+
/// \code
150+
/// __m128i _mm_sm3rnds2_epi32(__m128i __A, __m128i __B, __m128i __C, const int
151+
/// imm8) \endcode
152+
///
153+
/// This intrinsic corresponds to the \c VSM3RNDS2 instruction.
154+
///
155+
/// \param __A
156+
/// A 128-bit vector of [4 x int].
157+
/// \param __B
158+
/// A 128-bit vector of [4 x int].
159+
/// \param __C
160+
/// A 128-bit vector of [4 x int].
161+
/// \param imm8
162+
/// A 8-bit constant integer.
163+
/// \returns
164+
/// A 128-bit vector of [4 x int].
165+
///
166+
/// \code{.operation}
167+
/// DEFINE ROL32(dword, n) {
168+
/// count := n % 32
169+
/// dest := (dword << count) | (dword >> (32-count))
170+
/// RETURN dest
171+
/// }
172+
/// DEFINE P0(dword) {
173+
/// RETURN dword ^ ROL32(dword, 9) ^ ROL32(dword, 17)
174+
/// }
175+
/// DEFINE FF(x,y,z, round){
176+
/// IF round < 16
177+
/// RETURN (x ^ y ^ z)
178+
/// ELSE
179+
/// RETURN (x & y) | (x & z) | (y & z)
180+
/// FI
181+
/// }
182+
/// DEFINE GG(x, y, z, round){
183+
/// IF round < 16
184+
/// RETURN (x ^ y ^ z)
185+
/// ELSE
186+
/// RETURN (x & y) | (~x & z)
187+
/// FI
188+
/// }
189+
/// A[0] := __B.dword[3]
190+
/// B[0] := __B.dword[2]
191+
/// C[0] := __A.dword[3]
192+
/// D[0] := __A.dword[2]
193+
/// E[0] := __B.dword[1]
194+
/// F[0] := __B.dword[0]
195+
/// G[0] := __A.dword[1]
196+
/// H[0] := __A.dword[0]
197+
/// W[0] := __C.dword[0]
198+
/// W[1] := __C.dword[1]
199+
/// W[4] := __C.dword[2]
200+
/// W[5] := __C.dword[3]
201+
/// C[0] := ROL32(C[0], 9)
202+
/// D[0] := ROL32(D[0], 9)
203+
/// G[0] := ROL32(G[0], 19)
204+
/// H[0] := ROL32(H[0], 19)
205+
/// ROUND := __D & 0x3E
206+
/// IF ROUND < 16
207+
/// CONST := 0x79CC4519
208+
/// ELSE
209+
/// CONST := 0x7A879D8A
210+
/// FI
211+
/// CONST := ROL32(CONST,ROUND)
212+
/// FOR i:= 0 to 1
213+
/// S1 := ROL32((ROL32(A[i], 12) + E[i] + CONST), 7)
214+
/// S2 := S1 ^ ROL32(A[i], 12)
215+
/// T1 := FF(A[i], B[i], C[i], ROUND) + D[i] + S2 + (W[i] ^ W[i+4])
216+
/// T2 := GG(E[i], F[i], G[i], ROUND) + H[i] + S1 + W[i]
217+
/// D[i+1] := C[i]
218+
/// C[i+1] := ROL32(B[i],9)
219+
/// B[i+1] := A[i]
220+
/// A[i+1] := T1
221+
/// H[i+1] := G[i]
222+
/// G[i+1] := ROL32(F[i], 19)
223+
/// F[i+1] := E[i]
224+
/// E[i+1] := P0(T2)
225+
/// CONST := ROL32(CONST, 1)
226+
/// ENDFOR
227+
/// dst.dword[3] := A[2]
228+
/// dst.dword[2] := B[2]
229+
/// dst.dword[1] := E[2]
230+
/// dst.dword[0] := F[2]
231+
/// dst[MAX:128] := 0
232+
/// \endcode
233+
#define _mm_sm3rnds2_epi32(A, B, C, D) \
234+
(__m128i) __builtin_ia32_vsm3rnds2((__v4su)A, (__v4su)B, (__v4su)C, (int)D)
235+
236+
#undef __DEFAULT_FN_ATTRS128
237+
238+
#endif // __SM3INTRIN_H

‎clang/lib/Sema/SemaChecking.cpp

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@@ -6296,6 +6296,7 @@ bool Sema::CheckX86BuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
62966296
case X86::BI__builtin_ia32_pternlogq128_maskz:
62976297
case X86::BI__builtin_ia32_pternlogq256_mask:
62986298
case X86::BI__builtin_ia32_pternlogq256_maskz:
6299+
case X86::BI__builtin_ia32_vsm3rnds2:
62996300
i = 3; l = 0; u = 255;
63006301
break;
63016302
case X86::BI__builtin_ia32_gatherpfdpd:

‎clang/test/CodeGen/X86/sm3-builtins.c

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@@ -0,0 +1,22 @@
1+
// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +sm3 -emit-llvm -o - -Wall -Werror | FileCheck %s
2+
// RUN: %clang_cc1 %s -ffreestanding -triple=i386-unknown-unknown -target-feature +sm3 -emit-llvm -o - -Wall -Werror | FileCheck %s
3+
4+
#include <immintrin.h>
5+
6+
__m128i test_mm_sm3msg1_epi32(__m128i __A, __m128i __B, __m128i __C) {
7+
// CHECK-LABEL: @test_mm_sm3msg1_epi32(
8+
// CHECK: call <4 x i32> @llvm.x86.vsm3msg1(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}})
9+
return _mm_sm3msg1_epi32(__A, __B, __C);
10+
}
11+
12+
__m128i test_mm_sm3msg2_epi32(__m128i __A, __m128i __B, __m128i __C) {
13+
// CHECK-LABEL: @test_mm_sm3msg2_epi32(
14+
// CHECK: call <4 x i32> @llvm.x86.vsm3msg2(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}})
15+
return _mm_sm3msg2_epi32(__A, __B, __C);
16+
}
17+
18+
__m128i test_mm_sm3rnds2_epi32(__m128i __A, __m128i __B, __m128i __C) {
19+
// CHECK-LABEL: @test_mm_sm3rnds2_epi32(
20+
// CHECK: call <4 x i32> @llvm.x86.vsm3rnds2(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, i32 127)
21+
return _mm_sm3rnds2_epi32(__A, __B, __C, 127);
22+
}

‎clang/test/CodeGen/X86/sm3-error.c

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@@ -0,0 +1,7 @@
1+
// RUN: %clang_cc1 %s -ffreestanding -triple=i686-unknown-unknown -target-feature +sm3 -emit-llvm -fsyntax-only -verify
2+
3+
#include <immintrin.h>
4+
5+
__m128i test_mm_sm3rnds2_epi32(__m128i __A, __m128i __B, __m128i __C) {
6+
return _mm_sm3rnds2_epi32(__A, __B, __C, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}}
7+
}

‎clang/test/CodeGen/attr-target-x86.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -54,9 +54,9 @@ void __attribute__((target("arch=x86-64-v4"))) x86_64_v4(void) {}
5454
// CHECK: #0 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87" "tune-cpu"="i686"
5555
// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cmov,+crc32,+cx16,+cx8,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt"
5656
// CHECK-NOT: tune-cpu
57-
// CHECK: #2 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-aes,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-gfni,-kl,-pclmul,-sha,-sha512,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-widekl,-xop" "tune-cpu"="i686"
57+
// CHECK: #2 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-aes,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-gfni,-kl,-pclmul,-sha,-sha512,-sm3,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-widekl,-xop" "tune-cpu"="i686"
5858
// CHECK: #3 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+crc32,+cx8,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87" "tune-cpu"="i686"
59-
// CHECK: #4 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-sha512,-sse4.1,-sse4.2,-vaes,-vpclmulqdq,-xop" "tune-cpu"="i686"
59+
// CHECK: #4 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-sha512,-sm3,-sse4.1,-sse4.2,-vaes,-vpclmulqdq,-xop" "tune-cpu"="i686"
6060
// CHECK: #5 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cmov,+crc32,+cx16,+cx8,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt,-aes,-vaes"
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// CHECK-NOT: tune-cpu
6262
// CHECK: #6 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-3dnow,-3dnowa,-mmx"

‎clang/test/Driver/x86-target-features.c

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// SHA512: "-target-feature" "+sha512"
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// NO-SHA512: "-target-feature" "-sha512"
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357+
// RUN: %clang --target=i386 -msm3 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=SM3 %s
358+
// RUN: %clang --target=i386 -mno-sm3 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-SM3 %s
359+
// SM3: "-target-feature" "+sm3"
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// NO-SM3: "-target-feature" "-sm3"
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// RUN: %clang --target=i386 -march=i386 -mcrc32 %s -### 2>&1 | FileCheck -check-prefix=CRC32 %s
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// RUN: %clang --target=i386 -march=i386 -mno-crc32 %s -### 2>&1 | FileCheck -check-prefix=NO-CRC32 %s
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// CRC32: "-target-feature" "+crc32"

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