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[SPARC][IAS] Add SETX pseudoinstruction
This adds the v9 SETX pseudoinstruction for convenient loading of 64-bit values. Reviewed By: barannikov88 Differential Revision: https://reviews.llvm.org/D157230
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‎llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

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Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstBuilder.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCObjectFileInfo.h"
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#include "llvm/MC/MCParser/MCAsmLexer.h"
@@ -28,6 +29,7 @@
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/SMLoc.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/TargetParser/Triple.h"
@@ -119,6 +121,9 @@ class SparcAsmParser : public MCTargetAsmParser {
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bool expandSET(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions);
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bool expandSETX(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions);
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SMLoc getLoc() const { return getParser().getTok().getLoc(); }
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public:
@@ -643,6 +648,78 @@ bool SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc,
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return false;
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}
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bool SparcAsmParser::expandSETX(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions) {
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MCOperand MCRegOp = Inst.getOperand(0);
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MCOperand MCValOp = Inst.getOperand(1);
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MCOperand MCTmpOp = Inst.getOperand(2);
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assert(MCRegOp.isReg() && MCTmpOp.isReg());
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assert(MCValOp.isImm() || MCValOp.isExpr());
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// the imm operand can be either an expression or an immediate.
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bool IsImm = MCValOp.isImm();
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int64_t ImmValue = IsImm ? MCValOp.getImm() : 0;
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const MCExpr *ValExpr = IsImm ? MCConstantExpr::create(ImmValue, getContext())
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: MCValOp.getExpr();
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// Very small immediates can be expressed directly as a single `or`.
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if (IsImm && isInt<13>(ImmValue)) {
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// or rd, val, rd
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Instructions.push_back(MCInstBuilder(SP::ORri)
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.addReg(MCRegOp.getReg())
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.addReg(Sparc::G0)
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.addExpr(ValExpr));
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return false;
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}
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// Otherwise, first we set the lower half of the register.
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// sethi %hi(val), rd
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Instructions.push_back(
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MCInstBuilder(SP::SETHIi)
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.addReg(MCRegOp.getReg())
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.addExpr(adjustPICRelocation(SparcMCExpr::VK_Sparc_HI, ValExpr)));
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// or rd, %lo(val), rd
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Instructions.push_back(
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MCInstBuilder(SP::ORri)
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.addReg(MCRegOp.getReg())
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.addReg(MCRegOp.getReg())
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.addExpr(adjustPICRelocation(SparcMCExpr::VK_Sparc_LO, ValExpr)));
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// Small positive immediates can be expressed as a single `sethi`+`or`
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// combination, so we can just return here.
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if (IsImm && isUInt<32>(ImmValue))
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return false;
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// For bigger immediates, we need to generate the upper half, then shift and
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// merge it with the lower half that has just been generated above.
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// sethi %hh(val), tmp
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Instructions.push_back(
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MCInstBuilder(SP::SETHIi)
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.addReg(MCTmpOp.getReg())
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.addExpr(adjustPICRelocation(SparcMCExpr::VK_Sparc_HH, ValExpr)));
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// or tmp, %hm(val), tmp
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Instructions.push_back(
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MCInstBuilder(SP::ORri)
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.addReg(MCTmpOp.getReg())
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.addReg(MCTmpOp.getReg())
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.addExpr(adjustPICRelocation(SparcMCExpr::VK_Sparc_HM, ValExpr)));
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// sllx tmp, 32, tmp
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Instructions.push_back(MCInstBuilder(SP::SLLXri)
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.addReg(MCTmpOp.getReg())
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.addReg(MCTmpOp.getReg())
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.addImm(32));
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// or tmp, rd, rd
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Instructions.push_back(MCInstBuilder(SP::ORrr)
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.addReg(MCRegOp.getReg())
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.addReg(MCTmpOp.getReg())
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.addReg(MCRegOp.getReg()));
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return false;
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}
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bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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OperandVector &Operands,
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MCStreamer &Out,
@@ -663,6 +740,10 @@ bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
663740
if (expandSET(Inst, IDLoc, Instructions))
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return true;
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break;
743+
case SP::SETX:
744+
if (expandSETX(Inst, IDLoc, Instructions))
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return true;
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break;
666747
}
667748

668749
for (const MCInst &I : Instructions) {

‎llvm/lib/Target/Sparc/SparcInstrAliases.td

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -443,6 +443,13 @@ def : InstAlias<"save", (SAVErr G0, G0, G0)>;
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// def : InstAlias<"set $val, $rd", (ORri IntRegs:$rd, (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
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def SET : AsmPseudoInst<(outs IntRegs:$rd), (ins i32imm:$val), "set $val, $rd">;
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// setx value, tmp, rd
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// (turns into a sequence of sethi+or+shift, depending on the value)
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def SETX : AsmPseudoInst<(outs I64Regs:$rd),
449+
(ins i64imm:$val, I64Regs:$tmp),
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"setx $val, $tmp, $rd">,
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Requires<[Is64Bit, HasV9]>;
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// not rd -> xnor rd, %g0, rd
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def : InstAlias<"not $rd", (XNORrr IntRegs:$rd, IntRegs:$rd, G0), 0>;
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‎llvm/test/MC/Sparc/sparcv9-synthetic-instructions.s

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,80 @@
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! RUN: not llvm-mc %s -arch=sparc -show-encoding 2>&1 | FileCheck %s --check-prefix=V8
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! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: setx 1, %g1, %o1
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! V9: mov 1, %o1 ! encoding: [0x92,0x10,0x20,0x01]
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setx 1, %g1, %o1
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: setx (0+1), %g1, %o1
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! V9: mov 1, %o1 ! encoding: [0x92,0x10,0x20,0x01]
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setx (0+1), %g1, %o1
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: setx -1, %g1, %o1
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! V9: mov -1, %o1 ! encoding: [0x92,0x10,0x3f,0xff]
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setx -1, %g1, %o1
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: setx (0-1), %g1, %o1
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! V9: mov -1, %o1 ! encoding: [0x92,0x10,0x3f,0xff]
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setx (0-1), %g1, %o1
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: setx 0xffffffff, %g1, %o1
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! V9: sethi %hi(4294967295), %o1 ! encoding: [0x13,0b00AAAAAA,A,A]
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! V9: ! fixup A - offset: 0, value: %hi(4294967295), kind: fixup_sparc_hi22
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! V9: or %o1, %lo(4294967295), %o1 ! encoding: [0x92,0x12,0b011000AA,A]
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! V9: ! fixup A - offset: 0, value: %lo(4294967295), kind: fixup_sparc_lo10
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setx 0xffffffff, %g1, %o1
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: setx (0xffff0000+0x0000ffff), %g1, %o1
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! V9: sethi %hi(4294967295), %o1 ! encoding: [0x13,0b00AAAAAA,A,A]
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! V9: ! fixup A - offset: 0, value: %hi(4294967295), kind: fixup_sparc_hi22
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! V9: or %o1, %lo(4294967295), %o1 ! encoding: [0x92,0x12,0b011000AA,A]
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! V9: ! fixup A - offset: 0, value: %lo(4294967295), kind: fixup_sparc_lo10
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setx (0xffff0000+0x0000ffff), %g1, %o1
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40+
! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: setx 0x0123456789abcdef, %g1, %o0
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! V9: sethi %hi(81985529216486895), %o0 ! encoding: [0x11,0b00AAAAAA,A,A]
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! V9: ! fixup A - offset: 0, value: %hi(81985529216486895), kind: fixup_sparc_hi22
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! V9: or %o0, %lo(81985529216486895), %o0 ! encoding: [0x90,0x12,0b001000AA,A]
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! V9: ! fixup A - offset: 0, value: %lo(81985529216486895), kind: fixup_sparc_lo10
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! V9: sethi %hh(81985529216486895), %g1 ! encoding: [0x03,0b00AAAAAA,A,A]
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! V9: ! fixup A - offset: 0, value: %hh(81985529216486895), kind: fixup_sparc_hh
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! V9: or %g1, %hm(81985529216486895), %g1 ! encoding: [0x82,0x10,0b011000AA,A]
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! V9: ! fixup A - offset: 0, value: %hm(81985529216486895), kind: fixup_sparc_hm
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! V9: sllx %g1, 32, %g1 ! encoding: [0x83,0x28,0x70,0x20]
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! V9: or %g1, %o0, %o0 ! encoding: [0x90,0x10,0x40,0x08]
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setx 0x0123456789abcdef, %g1, %o0
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54+
! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: setx (0x0123456700000000+0x0000000089abcdef), %g1, %o0
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! V9: sethi %hi(81985529216486895), %o0 ! encoding: [0x11,0b00AAAAAA,A,A]
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! V9: ! fixup A - offset: 0, value: %hi(81985529216486895), kind: fixup_sparc_hi22
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! V9: or %o0, %lo(81985529216486895), %o0 ! encoding: [0x90,0x12,0b001000AA,A]
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! V9: ! fixup A - offset: 0, value: %lo(81985529216486895), kind: fixup_sparc_lo10
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! V9: sethi %hh(81985529216486895), %g1 ! encoding: [0x03,0b00AAAAAA,A,A]
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! V9: ! fixup A - offset: 0, value: %hh(81985529216486895), kind: fixup_sparc_hh
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! V9: or %g1, %hm(81985529216486895), %g1 ! encoding: [0x82,0x10,0b011000AA,A]
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! V9: ! fixup A - offset: 0, value: %hm(81985529216486895), kind: fixup_sparc_hm
64+
! V9: sllx %g1, 32, %g1 ! encoding: [0x83,0x28,0x70,0x20]
65+
! V9: or %g1, %o0, %o0 ! encoding: [0x90,0x10,0x40,0x08]
66+
setx (0x0123456700000000+0x0000000089abcdef), %g1, %o0
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68+
! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: setx (.BB1-.BB0), %g1, %o0
70+
! V9: sethi %hi(.BB1-.BB0), %o0 ! encoding: [0x11,0b00AAAAAA,A,A]
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! V9: ! fixup A - offset: 0, value: %hi(.BB1-.BB0), kind: fixup_sparc_hi22
72+
! V9: or %o0, %lo(.BB1-.BB0), %o0 ! encoding: [0x90,0x12,0b001000AA,A]
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! V9: ! fixup A - offset: 0, value: %lo(.BB1-.BB0), kind: fixup_sparc_lo10
74+
! V9: sethi %hh(.BB1-.BB0), %g1 ! encoding: [0x03,0b00AAAAAA,A,A]
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! V9: ! fixup A - offset: 0, value: %hh(.BB1-.BB0), kind: fixup_sparc_hh
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! V9: or %g1, %hm(.BB1-.BB0), %g1 ! encoding: [0x82,0x10,0b011000AA,A]
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! V9: ! fixup A - offset: 0, value: %hm(.BB1-.BB0), kind: fixup_sparc_hm
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! V9: sllx %g1, 32, %g1 ! encoding: [0x83,0x28,0x70,0x20]
79+
! V9: or %g1, %o0, %o0 ! encoding: [0x90,0x10,0x40,0x08]
80+
setx (.BB1-.BB0), %g1, %o0

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