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[AArch64][GlobalISel] Widen (<2 x s16> = G_BUILD_VECTOR) to <2 x s32>.
We don't support this as a argument or return type, it's always promoted to <2 x s32>. Performing the widening prevents us from having selection failures due to unsupported extends. Fixes llvm#58274
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4 files changed

+54
-21
lines changed

4 files changed

+54
-21
lines changed

‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -707,7 +707,6 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
707707
getActionDefinitionsBuilder(G_BUILD_VECTOR)
708708
.legalFor({{v8s8, s8},
709709
{v16s8, s8},
710-
{v2s16, s16},
711710
{v4s16, s16},
712711
{v8s16, s16},
713712
{v2s32, s32},
@@ -717,6 +716,9 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
717716
.clampNumElements(0, v4s32, v4s32)
718717
.clampNumElements(0, v2s64, v2s64)
719718
.minScalarOrElt(0, s8)
719+
.minScalarOrEltIf(
720+
[=](const LegalityQuery &Query) { return Query.Types[0] == v2s16; },
721+
0, s32)
720722
.minScalarSameAs(1, 0);
721723

722724
getActionDefinitionsBuilder(G_BUILD_VECTOR_TRUNC).lower();

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir

Lines changed: 31 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,9 @@ body: |
77
bb.0:
88
liveins: $w0, $w1, $w2, $w3
99
; CHECK-LABEL: name: legal_v4s32
10-
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
10+
; CHECK: liveins: $w0, $w1, $w2, $w3
11+
; CHECK-NEXT: {{ $}}
12+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
1113
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
1214
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
1315
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $w3
@@ -28,7 +30,9 @@ body: |
2830
bb.0:
2931
liveins: $x0, $x1
3032
; CHECK-LABEL: name: legal_v2s64
31-
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
33+
; CHECK: liveins: $x0, $x1
34+
; CHECK-NEXT: {{ $}}
35+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
3236
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
3337
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[COPY1]](s64)
3438
; CHECK-NEXT: $q0 = COPY [[BUILD_VECTOR]](<2 x s64>)
@@ -45,7 +49,9 @@ body: |
4549
bb.0:
4650
liveins: $x0, $x1
4751
; CHECK-LABEL: name: legal_v2p0
48-
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
52+
; CHECK: liveins: $x0, $x1
53+
; CHECK-NEXT: {{ $}}
54+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
4955
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
5056
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[COPY]](p0), [[COPY1]](p0)
5157
; CHECK-NEXT: $q0 = COPY [[BUILD_VECTOR]](<2 x p0>)
@@ -105,3 +111,25 @@ body: |
105111
$q0 = COPY %w(<16 x s8>)
106112
RET_ReallyLR
107113
...
114+
---
115+
name: widen_v2s16
116+
body: |
117+
bb.0:
118+
liveins: $x0, $x1
119+
; CHECK-LABEL: name: widen_v2s16
120+
; CHECK: liveins: $x0, $x1
121+
; CHECK-NEXT: {{ $}}
122+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
123+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $h1
124+
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s16)
125+
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY1]](s16)
126+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32)
127+
; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<2 x s32>)
128+
; CHECK-NEXT: RET_ReallyLR
129+
%0:_(s16) = COPY $h0
130+
%1:_(s16) = COPY $h1
131+
%2:_(<2 x s16>) = G_BUILD_VECTOR %0(s16), %1(s16)
132+
%ext:_(<2 x s32>) = G_ANYEXT %2(<2 x s16>)
133+
$d0 = COPY %ext(<2 x s32>)
134+
RET_ReallyLR
135+
...

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir

Lines changed: 14 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,9 @@ body: |
77
liveins: $x0
88
99
; CHECK-LABEL: name: test_load
10-
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
10+
; CHECK: liveins: $x0
11+
; CHECK-NEXT: {{ $}}
12+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
1113
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (load (s8))
1214
; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[LOAD]], 1
1315
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASSERT_ZEXT]](s8)
@@ -62,7 +64,9 @@ body: |
6264
liveins: $x0, $w1
6365
6466
; CHECK-LABEL: name: test_store
65-
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
67+
; CHECK: liveins: $x0, $w1
68+
; CHECK-NEXT: {{ $}}
69+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
6670
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
6771
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
6872
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
@@ -518,7 +522,9 @@ body: |
518522
liveins: $x0, $w1
519523
520524
; CHECK-LABEL: name: test_trunc_store
521-
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
525+
; CHECK: liveins: $x0, $w1
526+
; CHECK-NEXT: {{ $}}
527+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
522528
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
523529
; CHECK-NEXT: %val64:_(s64) = COPY $x2
524530
; CHECK-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s8))
@@ -599,8 +605,11 @@ body: |
599605
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
600606
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
601607
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 2)
602-
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[LOAD]](s16), [[LOAD1]](s16)
603-
; CHECK-NEXT: $s0 = COPY [[BUILD_VECTOR]](<2 x s16>)
608+
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s16)
609+
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD1]](s16)
610+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32)
611+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[BUILD_VECTOR]](<2 x s32>)
612+
; CHECK-NEXT: $s0 = COPY [[TRUNC]](<2 x s16>)
604613
; CHECK-NEXT: RET_ReallyLR
605614
%0:_(p0) = COPY $x0
606615
%1(<2 x s16>) = G_LOAD %0(p0) :: (load (<2 x s16>))

‎llvm/test/CodeGen/AArch64/GlobalISel/select-unmerge.mir

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -109,26 +109,20 @@ body: |
109109
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.ssub
110110
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[INSERT_SUBREG]].hsub
111111
; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG]], 1
112-
; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
113-
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.hsub
114-
; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
115-
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[DUPi16_]], %subreg.hsub
116-
; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG1]], 1, [[INSERT_SUBREG2]], 0
117-
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY [[INSvi16lane]].ssub
118-
; CHECK-NEXT: $s0 = COPY [[COPY2]]
119-
; CHECK-NEXT: RET_ReallyLR implicit $s0
112+
; CHECK-NEXT: $h0 = COPY [[COPY1]]
113+
; CHECK-NEXT: $h1 = COPY [[DUPi16_]]
114+
; CHECK-NEXT: RET_ReallyLR implicit $h0, implicit $h1
120115
%0:fpr(<2 x s16>) = COPY $s0
121116
122117
; Since 2 * 16 != 128, we need to widen using implicit defs.
123118
; Note that we expect to reuse one of the INSERT_SUBREG results, as CPYi16
124119
; expects a lane > 0.
125120
%2:fpr(s16), %3:fpr(s16) = G_UNMERGE_VALUES %0(<2 x s16>)
126121
127-
%1:fpr(<2 x s16>) = G_BUILD_VECTOR %2(s16), %3(s16)
122+
$h0 = COPY %2(s16)
123+
$h1 = COPY %3(s16)
128124
129-
$s0 = COPY %1(<2 x s16>)
130-
131-
RET_ReallyLR implicit $s0
125+
RET_ReallyLR implicit $h0, implicit $h1
132126
...
133127
---
134128
name: test_v4s16_unmerge

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