Skip to content

Commit d8faf03

Browse files
tianqingwtianqingw
committed
[X86] Add -mgeneral-regs-only support.
Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D103943
1 parent a2a4bc5 commit d8faf03

File tree

5 files changed

+80
-7
lines changed

5 files changed

+80
-7
lines changed

‎clang/include/clang/Driver/Options.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3207,8 +3207,8 @@ defm aapcs_bitfield_width : BoolOption<"f", "aapcs-bitfield-width",
32073207
" volatile bit-field width is dictated by the field container type. (ARM only).">>,
32083208
Group<m_arm_Features_Group>;
32093209

3210-
def mgeneral_regs_only : Flag<["-"], "mgeneral-regs-only">, Group<m_aarch64_Features_Group>,
3211-
HelpText<"Generate code which only uses the general purpose registers (AArch64 only)">;
3210+
def mgeneral_regs_only : Flag<["-"], "mgeneral-regs-only">, Group<m_Group>,
3211+
HelpText<"Generate code which only uses the general purpose registers (AArch64/x86 only)">;
32123212
def mfix_cortex_a53_835769 : Flag<["-"], "mfix-cortex-a53-835769">,
32133213
Group<m_aarch64_Features_Group>,
32143214
HelpText<"Workaround Cortex-A53 erratum 835769 (AArch64 only)">;

‎clang/lib/Basic/Targets/X86.cpp

Lines changed: 18 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -117,7 +117,20 @@ bool X86TargetInfo::initFeatureMap(
117117
for (auto &F : CPUFeatures)
118118
setFeatureEnabled(Features, F, true);
119119

120-
if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
120+
std::vector<std::string> UpdatedFeaturesVec;
121+
for (const auto &Feature : FeaturesVec) {
122+
// Expand general-regs-only to -x86, -mmx and -sse
123+
if (Feature == "+general-regs-only") {
124+
UpdatedFeaturesVec.push_back("-x87");
125+
UpdatedFeaturesVec.push_back("-mmx");
126+
UpdatedFeaturesVec.push_back("-sse");
127+
continue;
128+
}
129+
130+
UpdatedFeaturesVec.push_back(Feature);
131+
}
132+
133+
if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec))
121134
return false;
122135

123136
// Can't do this earlier because we need to be able to explicitly enable
@@ -126,20 +139,20 @@ bool X86TargetInfo::initFeatureMap(
126139
// Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
127140
auto I = Features.find("sse4.2");
128141
if (I != Features.end() && I->getValue() &&
129-
llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end())
142+
llvm::find(UpdatedFeaturesVec, "-popcnt") == UpdatedFeaturesVec.end())
130143
Features["popcnt"] = true;
131144

132145
// Additionally, if SSE is enabled and mmx is not explicitly disabled,
133146
// then enable MMX.
134147
I = Features.find("sse");
135148
if (I != Features.end() && I->getValue() &&
136-
llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end())
149+
llvm::find(UpdatedFeaturesVec, "-mmx") == UpdatedFeaturesVec.end())
137150
Features["mmx"] = true;
138151

139152
// Enable xsave if avx is enabled and xsave is not explicitly disabled.
140153
I = Features.find("avx");
141154
if (I != Features.end() && I->getValue() &&
142-
llvm::find(FeaturesVec, "-xsave") == FeaturesVec.end())
155+
llvm::find(UpdatedFeaturesVec, "-xsave") == UpdatedFeaturesVec.end())
143156
Features["xsave"] = true;
144157

145158
return true;
@@ -866,6 +879,7 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
866879
.Case("fma4", true)
867880
.Case("fsgsbase", true)
868881
.Case("fxsr", true)
882+
.Case("general-regs-only", true)
869883
.Case("gfni", true)
870884
.Case("hreset", true)
871885
.Case("invpcid", true)

‎clang/lib/Driver/ToolChains/Arch/X86.cpp

Lines changed: 20 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -213,5 +213,24 @@ void x86::getX86TargetFeatures(const Driver &D, const llvm::Triple &Triple,
213213

214214
// Now add any that the user explicitly requested on the command line,
215215
// which may override the defaults.
216-
handleTargetFeaturesGroup(Args, Features, options::OPT_m_x86_Features_Group);
216+
for (const Arg *A : Args.filtered(options::OPT_m_x86_Features_Group,
217+
options::OPT_mgeneral_regs_only)) {
218+
StringRef Name = A->getOption().getName();
219+
A->claim();
220+
221+
// Skip over "-m".
222+
assert(Name.startswith("m") && "Invalid feature name.");
223+
Name = Name.substr(1);
224+
225+
// Replace -mgeneral-regs-only with -x87, -mmx, -sse
226+
if (A->getOption().getID() == options::OPT_mgeneral_regs_only) {
227+
Features.insert(Features.end(), {"-x87", "-mmx", "-sse"});
228+
continue;
229+
}
230+
231+
bool IsNegative = Name.startswith("no-");
232+
if (IsNegative)
233+
Name = Name.substr(3);
234+
Features.push_back(Args.MakeArgString((IsNegative ? "-" : "+") + Name));
235+
}
217236
}

‎clang/test/CodeGen/attr-target-general-regs-only-x86.c

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
// Test general-regs-only target attribute on x86
2+
3+
// RUN: %clang_cc1 -triple i386-unknown-linux-gnu -emit-llvm %s -o - | FileCheck %s
4+
// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm %s -o - | FileCheck %s
5+
6+
// CHECK: define{{.*}} void @f() [[GPR_ATTRS:#[0-9]+]]
7+
void __attribute__((target("general-regs-only"))) f() { }
8+
// CHECK: define{{.*}} void @f_before() [[GPR_ATTRS:#[0-9]+]]
9+
void __attribute__((target("avx2,general-regs-only"))) f_before() { }
10+
// CHECK: define{{.*}} void @f_after() [[AVX2_ATTRS:#[0-9]+]]
11+
void __attribute__((target("general-regs-only,avx2"))) f_after() { }
12+
13+
// CHECK: attributes [[GPR_ATTRS]] = { {{.*}} "target-features"="{{.*}}-avx{{.*}}-avx2{{.*}}-avx512f{{.*}}-sse{{.*}}-sse2{{.*}}-ssse3{{.*}}-x87{{.*}}"
14+
// CHECK: attributes [[AVX2_ATTRS]] = { {{.*}} "target-features"="{{.*}}+avx{{.*}}+avx2{{.*}}+sse{{.*}}+sse2{{.*}}+ssse3{{.*}}-avx512f{{.*}}-x87{{.*}}"

‎clang/test/Driver/x86-mgeneral-regs-only.c

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
// Test the -mgeneral-regs-only option on x86
2+
3+
// RUN: %clang -target i386-unknown-linux-gnu -mgeneral-regs-only %s -### 2>&1 | FileCheck --check-prefix=CMD %s
4+
// RUN: %clang -target x86_64-unknown-linux-gnu -mgeneral-regs-only %s -### 2>&1 | FileCheck --check-prefix=CMD %s
5+
// RUN: %clang -target i386-unknown-linux-gnu -mavx2 -mgeneral-regs-only %s -### 2>&1 | FileCheck --check-prefixes=CMD,CMD-BEFORE %s
6+
// RUN: %clang -target x86_64-unknown-linux-gnu -mavx2 -mgeneral-regs-only %s -### 2>&1 | FileCheck --check-prefixes=CMD,CMD-BEFORE %s
7+
// RUN: %clang -target i386-unknown-linux-gnu -mgeneral-regs-only -mavx2 %s -### 2>&1 | FileCheck --check-prefixes=CMD,CMD-AFTER %s
8+
// RUN: %clang -target x86_64-unknown-linux-gnu -mgeneral-regs-only -mavx2 %s -### 2>&1 | FileCheck --check-prefixes=CMD,CMD-AFTER %s
9+
10+
// RUN: %clang -target i386-unknown-linux-gnu -mgeneral-regs-only -S -emit-llvm %s -o - 2>&1 | FileCheck --check-prefix=IR-GPR %s
11+
// RUN: %clang -target x86_64-unknown-linux-gnu -mgeneral-regs-only -S -emit-llvm %s -o - 2>&1 | FileCheck --check-prefix=IR-GPR %s
12+
// RUN: %clang -target i386-unknown-linux-gnu -mavx2 -mgeneral-regs-only -S -emit-llvm %s -o - 2>&1 | FileCheck --check-prefix=IR-GPR %s
13+
// RUN: %clang -target x86_64-unknown-linux-gnu -mavx2 -mgeneral-regs-only -S -emit-llvm %s -o - 2>&1 | FileCheck --check-prefix=IR-GPR %s
14+
// RUN: %clang -target i386-unknown-linux-gnu -mgeneral-regs-only -mavx2 -S -emit-llvm %s -o - 2>&1 | FileCheck --check-prefix=IR-AVX2 %s
15+
// RUN: %clang -target x86_64-unknown-linux-gnu -mgeneral-regs-only -mavx2 -S -emit-llvm %s -o - 2>&1 | FileCheck --check-prefix=IR-AVX2 %s
16+
17+
// CMD-BEFORE: "-target-feature" "+avx2"
18+
// CMD: "-target-feature" "-x87"
19+
// CMD: "-target-feature" "-mmx"
20+
// CMD: "-target-feature" "-sse"
21+
// CMD-AFTER: "-target-feature" "+avx2"
22+
23+
void foo() { }
24+
25+
// IR-GPR: attributes {{.*}} = { {{.*}} "target-features"="{{.*}}-avx{{.*}}-avx2{{.*}}-avx512f{{.*}}-sse{{.*}}-sse2{{.*}}-ssse3{{.*}}-x87{{.*}}"
26+
// IR-AVX2: attributes {{.*}} = { {{.*}} "target-features"="{{.*}}+avx{{.*}}+avx2{{.*}}+sse{{.*}}+sse2{{.*}}+ssse3{{.*}}-avx512f{{.*}}-x87{{.*}}"

0 commit comments

Comments
 (0)