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[flang] Add PowerPC vec_stxvp and vsx_stxvp intrinsic
Differential Revision: https://reviews.llvm.org/D157768
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‎flang/include/flang/Optimizer/Builder/PPCIntrinsicCall.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,7 @@ enum class VecOp {
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St,
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Ste,
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Stxv,
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Stxvp,
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Sub,
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Xor,
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Xst,

‎flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp

Lines changed: 18 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -223,6 +223,11 @@ static constexpr IntrinsicHandler ppcHandlers[]{
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&PI::genVecXStore<VecOp::Stxv>),
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{{{"arg1", asValue}, {"arg2", asValue}, {"arg3", asAddr}}},
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/*isElemental=*/false},
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{"__ppc_vec_stxvp",
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static_cast<IntrinsicLibrary::SubroutineGenerator>(
228+
&PI::genVecStore<VecOp::Stxvp>),
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{{{"arg1", asValue}, {"arg2", asValue}, {"arg3", asAddr}}},
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/*isElemental=*/false},
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{"__ppc_vec_sub",
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static_cast<IntrinsicLibrary::ExtendedGenerator>(
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&PI::genVecAddAndMulSubXor<VecOp::Sub>),
@@ -1788,6 +1793,11 @@ void PPCIntrinsicLibrary::genVecStore(llvm::ArrayRef<fir::ExtendedValue> args) {
17881793
assert(false && "unknown type");
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break;
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}
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case VecOp::Stxvp:
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// __vector_pair type
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stTy = mlir::VectorType::get(256, mlir::IntegerType::get(context, 1));
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fname = "llvm.ppc.vsx.stxvp";
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break;
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default:
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llvm_unreachable("invalid vector operation for generator");
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}
@@ -1798,11 +1808,18 @@ void PPCIntrinsicLibrary::genVecStore(llvm::ArrayRef<fir::ExtendedValue> args) {
17981808

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llvm::SmallVector<mlir::Value, 4> biArgs;
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1801-
mlir::Value newArg1;
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if (vop == VecOp::Stxvp) {
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biArgs.push_back(argBases[0]);
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biArgs.push_back(addr);
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builder.create<fir::CallOp>(loc, funcOp, biArgs);
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return;
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}
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18021818
auto vecTyInfo{getVecTypeFromFirType(argBases[0].getType())};
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auto cnv{builder.createConvert(loc, vecTyInfo.toMlirVectorType(context),
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argBases[0])};
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1822+
mlir::Value newArg1{nullptr};
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if (stTy != arg1TyInfo.toMlirVectorType(context))
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newArg1 = builder.create<mlir::vector::BitCastOp>(loc, stTy, cnv);
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else

‎flang/module/__ppc_intrinsics.f90

Lines changed: 112 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -384,13 +384,76 @@ pure subroutine sub_vr##VKIND##ir##VKIND(arg1, arg2, arg3); \
384384
!dir$ ignore_tkr(r) arg3; \
385385
end subroutine ;
386386

387+
! subroutine(__vector_pair, i, __vector_pair)
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pure subroutine sub_vpi0vp(arg1, arg2, arg3)
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__vector_pair, intent(in) :: arg1
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integer(8), intent(in) :: arg2
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!dir$ ignore_tkr(k) arg2
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__vector_pair, intent(out) :: arg3
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!dir$ ignore_tkr(r) arg3
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end subroutine
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! subroutine(__vector_pair, i, vector(i))
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#define SUB_VPI0VI(VKIND) \
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pure subroutine sub_vpi0vi##VKIND(arg1, arg2, arg3); \
399+
__vector_pair, intent(in) :: arg1; \
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integer(8), intent(in) :: arg2; \
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!dir$ ignore_tkr(k) arg2; \
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vector(integer(VKIND)), intent(out) :: arg3; \
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!dir$ ignore_tkr(r) arg3; \
404+
end subroutine;
405+
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! subroutine(__vector_pair, i, vector(u))
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#define SUB_VPI0VU(VKIND) \
408+
pure subroutine sub_vpi0vu##VKIND(arg1, arg2, arg3); \
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__vector_pair, intent(in) :: arg1; \
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integer(8), intent(in) :: arg2; \
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!dir$ ignore_tkr(k) arg2; \
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vector(unsigned(VKIND)), intent(out) :: arg3; \
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!dir$ ignore_tkr(r) arg3; \
414+
end subroutine;
415+
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! subroutine(__vector_pair, i, vector(r))
417+
#define SUB_VPI0VR(VKIND) \
418+
pure subroutine sub_vpi0vr##VKIND(arg1, arg2, arg3); \
419+
__vector_pair, intent(in) :: arg1; \
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integer(8), intent(in) :: arg2; \
421+
!dir$ ignore_tkr(k) arg2; \
422+
vector(real(VKIND)), intent(out) :: arg3; \
423+
!dir$ ignore_tkr(r) arg3; \
424+
end subroutine;
425+
426+
! subroutine(__vector_pair, i, i)
427+
pure subroutine sub_vpi0i0(arg1, arg2, arg3)
428+
__vector_pair, intent(in) :: arg1
429+
integer(8), intent(in) :: arg2
430+
!dir$ ignore_tkr(k) arg2
431+
integer(8), intent(out) :: arg3
432+
!dir$ ignore_tkr(kr) arg3
433+
end subroutine
434+
435+
! subroutine(__vector_pair, i, r)
436+
pure subroutine sub_vpi0r0(arg1, arg2, arg3)
437+
__vector_pair, intent(in) :: arg1
438+
integer(8), intent(in) :: arg2
439+
!dir$ ignore_tkr(k) arg2
440+
real(8), intent(out) :: arg3
441+
!dir$ ignore_tkr(kr) arg3
442+
end subroutine
443+
387444
SUB_VIIVI(1) SUB_VIIVI(2) SUB_VIIVI(4) SUB_VIIVI(8)
388445
SUB_VUIVU(1) SUB_VUIVU(2) SUB_VUIVU(4) SUB_VUIVU(8)
389446
SUB_VRIVR(4) SUB_VRIVR(8)
390447
SUB_VIII(1) SUB_VIII(2) SUB_VIII(4) SUB_VIII(8)
391448
SUB_VUII(1) SUB_VUII(2) SUB_VUII(4) SUB_VUII(8)
392449
SUB_VRIR(4) SUB_VRIR(8)
450+
SUB_VPI0VI(1) SUB_VPI0VI(2) SUB_VPI0VI(4) SUB_VPI0VI(8)
451+
SUB_VPI0VU(1) SUB_VPI0VU(2) SUB_VPI0VU(4) SUB_VPI0VU(8)
452+
SUB_VPI0VR(4) SUB_VPI0VR(8)
393453

454+
#undef SUB_VPI0VR
455+
#undef SUB_VPI0VU
456+
#undef SUB_VPI0VI
394457
#undef SUB_VRIR
395458
#undef SUB_VUII
396459
#undef SUB_VIII
@@ -1328,4 +1391,53 @@ end function func_r8r8i
13281391
#undef SUB_VU_I_I
13291392
#undef SUB_VR_Ik_R
13301393

1394+
!-----------------------------------------------------------------------
1395+
! subroutine(__vector_pair, integer, __vector_pair/vector/integer/real)
1396+
!-----------------------------------------------------------------------
1397+
#define VP_I0_VI(NAME, VKIND) __ppc_##NAME##_vpi0vi##VKIND
1398+
#define VP_I0_VU(NAME, VKIND) __ppc_##NAME##_vpi0vu##VKIND
1399+
#define VP_I0_VR(NAME, VKIND) __ppc_##NAME##_vpi0vr##VKIND
1400+
1401+
#define VEC_VP_I0_VI(NAME, VKIND) \
1402+
procedure(sub_vpi0vi##VKIND) :: VP_I0_VI(NAME, VKIND);
1403+
#define VEC_VP_I0_VU(NAME, VKIND) \
1404+
procedure(sub_vpi0vu##VKIND) :: VP_I0_VU(NAME, VKIND);
1405+
#define VEC_VP_I0_VR(NAME, VKIND) \
1406+
procedure(sub_vpi0vr##VKIND) :: VP_I0_VR(NAME, VKIND);
1407+
1408+
! vec_stxvp
1409+
procedure(sub_vpi0vp) :: __ppc_vec_stxvp_vpi0vp0
1410+
procedure(sub_vpi0i0) :: __ppc_vec_stxvp_vpi0i0
1411+
procedure(sub_vpi0r0) :: __ppc_vec_stxvp_vpi0r0
1412+
VEC_VP_I0_VI(vec_stxvp, 1) VEC_VP_I0_VI(vec_stxvp, 2) VEC_VP_I0_VI(vec_stxvp, 4) VEC_VP_I0_VI(vec_stxvp, 8)
1413+
VEC_VP_I0_VU(vec_stxvp, 1) VEC_VP_I0_VU(vec_stxvp, 2) VEC_VP_I0_VU(vec_stxvp, 4) VEC_VP_I0_VU(vec_stxvp, 8)
1414+
VEC_VP_I0_VR(vec_stxvp, 4) VEC_VP_I0_VR(vec_stxvp, 8)
1415+
interface vec_stxvp
1416+
procedure :: __ppc_vec_stxvp_vpi0vp0
1417+
procedure :: __ppc_vec_stxvp_vpi0i0
1418+
procedure :: __ppc_vec_stxvp_vpi0r0
1419+
procedure :: VP_I0_VI(vec_stxvp, 1), VP_I0_VI(vec_stxvp, 2), VP_I0_VI(vec_stxvp, 4), VP_I0_VI(vec_stxvp, 8)
1420+
procedure :: VP_I0_VU(vec_stxvp, 1), VP_I0_VU(vec_stxvp, 2), VP_I0_VU(vec_stxvp, 4), VP_I0_VU(vec_stxvp, 8)
1421+
procedure :: VP_I0_VR(vec_stxvp, 4), VP_I0_VR(vec_stxvp, 8)
1422+
end interface vec_stxvp
1423+
public :: vec_stxvp
1424+
1425+
! vsx_stxvp (alias to vec_stxvp)
1426+
interface vsx_stxvp
1427+
procedure :: __ppc_vec_stxvp_vpi0vp0
1428+
procedure :: __ppc_vec_stxvp_vpi0i0
1429+
procedure :: __ppc_vec_stxvp_vpi0r0
1430+
procedure :: VP_I0_VI(vec_stxvp, 1), VP_I0_VI(vec_stxvp, 2), VP_I0_VI(vec_stxvp, 4), VP_I0_VI(vec_stxvp, 8)
1431+
procedure :: VP_I0_VU(vec_stxvp, 1), VP_I0_VU(vec_stxvp, 2), VP_I0_VU(vec_stxvp, 4), VP_I0_VU(vec_stxvp, 8)
1432+
procedure :: VP_I0_VR(vec_stxvp, 4), VP_I0_VR(vec_stxvp, 8)
1433+
end interface vsx_stxvp
1434+
public :: vsx_stxvp
1435+
1436+
#undef VEC_VP_I0_VR
1437+
#undef VEC_VP_I0_VU
1438+
#undef VEC_VP_I0_VI
1439+
#undef VP_I0_VR
1440+
#undef VP_I0_VU
1441+
#undef VP_I0_VI
1442+
13311443
end module __ppc_intrinsics

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