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Petar AvramovicPetar Avramovic
Petar Avramovic
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Petar Avramovic
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[MIPS GlobalISel] Regbanks for G_SELECT. Select i64, f32 and f64 select
Select gprb or fprb when def/use register operand of G_SELECT is used/defined by either: copy to/from physical register or instruction with only one mapping available for that use/def operand. Integer s64 select is handled with narrowScalar when mapping is applied, produced artifacts are combined away. Manually set gprb to all register operands of instructions created during narrowScalar. For selection of floating point s32 or s64 select it is enough to set fprb of appropriate size and selectImpl will do the rest. Differential Revision: https://reviews.llvm.org/D64350 llvm-svn: 365492
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6 files changed

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-30
lines changed

6 files changed

+449
-30
lines changed

‎llvm/lib/Target/Mips/MipsLegalizerInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,7 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
5555
.minScalar(0, s32);
5656

5757
getActionDefinitionsBuilder(G_SELECT)
58-
.legalForCartesianProduct({p0, s32}, {s32})
58+
.legalForCartesianProduct({p0, s32, s64}, {s32})
5959
.minScalar(0, s32)
6060
.minScalar(1, s32);
6161

‎llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp

Lines changed: 34 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -194,6 +194,13 @@ MipsRegisterBankInfo::AmbiguousRegDefUseContainer::AmbiguousRegDefUseContainer(
194194

195195
if (MI->getOpcode() == TargetOpcode::G_STORE)
196196
addUseDef(MI->getOperand(0).getReg(), MRI);
197+
198+
if (MI->getOpcode() == TargetOpcode::G_SELECT) {
199+
addDefUses(MI->getOperand(0).getReg(), MRI);
200+
201+
addUseDef(MI->getOperand(2).getReg(), MRI);
202+
addUseDef(MI->getOperand(3).getReg(), MRI);
203+
}
197204
}
198205

199206
bool MipsRegisterBankInfo::TypeInfoForMF::visit(const MachineInstr *MI) {
@@ -377,6 +384,31 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
377384
}
378385
break;
379386
}
387+
case G_SELECT: {
388+
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
389+
InstType InstTy = InstType::Integer;
390+
if (!MRI.getType(MI.getOperand(0).getReg()).isPointer()) {
391+
InstTy = TI.determineInstType(&MI);
392+
}
393+
394+
if (InstTy == InstType::FloatingPoint) { // fprb
395+
const RegisterBankInfo::ValueMapping *Bank =
396+
Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
397+
: &Mips::ValueMappings[Mips::DPRIdx];
398+
OperandsMapping = getOperandsMapping(
399+
{Bank, &Mips::ValueMappings[Mips::GPRIdx], Bank, Bank});
400+
break;
401+
} else { // gprb
402+
const RegisterBankInfo::ValueMapping *Bank =
403+
Size <= 32 ? &Mips::ValueMappings[Mips::GPRIdx]
404+
: &Mips::ValueMappings[Mips::DPRIdx];
405+
OperandsMapping = getOperandsMapping(
406+
{Bank, &Mips::ValueMappings[Mips::GPRIdx], Bank, Bank});
407+
if (Size == 64)
408+
MappingID = CustomMappingID;
409+
}
410+
break;
411+
}
380412
case G_UNMERGE_VALUES: {
381413
OperandsMapping = getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx],
382414
&Mips::ValueMappings[Mips::GPRIdx],
@@ -468,13 +500,6 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
468500
&Mips::ValueMappings[Mips::GPRIdx],
469501
&Mips::ValueMappings[Mips::GPRIdx]});
470502
break;
471-
case G_SELECT:
472-
OperandsMapping =
473-
getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx],
474-
&Mips::ValueMappings[Mips::GPRIdx],
475-
&Mips::ValueMappings[Mips::GPRIdx],
476-
&Mips::ValueMappings[Mips::GPRIdx]});
477-
break;
478503
default:
479504
return getInvalidInstructionMapping();
480505
}
@@ -519,7 +544,8 @@ void MipsRegisterBankInfo::applyMappingImpl(
519544

520545
switch (MI.getOpcode()) {
521546
case TargetOpcode::G_LOAD:
522-
case TargetOpcode::G_STORE: {
547+
case TargetOpcode::G_STORE:
548+
case TargetOpcode::G_SELECT: {
523549
Helper.narrowScalar(MI, 0, LLT::scalar(32));
524550
// Handle new instructions.
525551
while (!NewInstrs.empty()) {

‎llvm/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir

Lines changed: 131 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,12 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
2+
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32FP32
3+
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32FP64
34
--- |
45

56
define void @select_i32() {entry: ret void}
67
define void @select_ptr() {entry: ret void}
8+
define void @select_float() {entry: ret void}
9+
define void @select_double() {entry: ret void}
710

811
...
912
---
@@ -16,16 +19,26 @@ body: |
1619
bb.1.entry:
1720
liveins: $a0, $a1, $a2
1821
19-
; MIPS32-LABEL: name: select_i32
20-
; MIPS32: liveins: $a0, $a1, $a2
21-
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
22-
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
23-
; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
24-
; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
25-
; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
26-
; MIPS32: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[AND]], [[COPY2]]
27-
; MIPS32: $v0 = COPY [[MOVN_I_I]]
28-
; MIPS32: RetRA implicit $v0
22+
; MIPS32FP32-LABEL: name: select_i32
23+
; MIPS32FP32: liveins: $a0, $a1, $a2
24+
; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
25+
; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
26+
; MIPS32FP32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
27+
; MIPS32FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
28+
; MIPS32FP32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
29+
; MIPS32FP32: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[AND]], [[COPY2]]
30+
; MIPS32FP32: $v0 = COPY [[MOVN_I_I]]
31+
; MIPS32FP32: RetRA implicit $v0
32+
; MIPS32FP64-LABEL: name: select_i32
33+
; MIPS32FP64: liveins: $a0, $a1, $a2
34+
; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
35+
; MIPS32FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
36+
; MIPS32FP64: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
37+
; MIPS32FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
38+
; MIPS32FP64: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
39+
; MIPS32FP64: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[AND]], [[COPY2]]
40+
; MIPS32FP64: $v0 = COPY [[MOVN_I_I]]
41+
; MIPS32FP64: RetRA implicit $v0
2942
%3:gprb(s32) = COPY $a0
3043
%1:gprb(s32) = COPY $a1
3144
%2:gprb(s32) = COPY $a2
@@ -47,16 +60,26 @@ body: |
4760
bb.1.entry:
4861
liveins: $a0, $a1, $a2
4962
50-
; MIPS32-LABEL: name: select_ptr
51-
; MIPS32: liveins: $a0, $a1, $a2
52-
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
53-
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
54-
; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
55-
; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
56-
; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
57-
; MIPS32: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[AND]], [[COPY2]]
58-
; MIPS32: $v0 = COPY [[MOVN_I_I]]
59-
; MIPS32: RetRA implicit $v0
63+
; MIPS32FP32-LABEL: name: select_ptr
64+
; MIPS32FP32: liveins: $a0, $a1, $a2
65+
; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
66+
; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
67+
; MIPS32FP32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
68+
; MIPS32FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
69+
; MIPS32FP32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
70+
; MIPS32FP32: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[AND]], [[COPY2]]
71+
; MIPS32FP32: $v0 = COPY [[MOVN_I_I]]
72+
; MIPS32FP32: RetRA implicit $v0
73+
; MIPS32FP64-LABEL: name: select_ptr
74+
; MIPS32FP64: liveins: $a0, $a1, $a2
75+
; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
76+
; MIPS32FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
77+
; MIPS32FP64: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
78+
; MIPS32FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
79+
; MIPS32FP64: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
80+
; MIPS32FP64: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[AND]], [[COPY2]]
81+
; MIPS32FP64: $v0 = COPY [[MOVN_I_I]]
82+
; MIPS32FP64: RetRA implicit $v0
6083
%3:gprb(s32) = COPY $a0
6184
%1:gprb(p0) = COPY $a1
6285
%2:gprb(p0) = COPY $a2
@@ -68,3 +91,90 @@ body: |
6891
RetRA implicit $v0
6992
7093
...
94+
---
95+
name: select_float
96+
alignment: 2
97+
legalized: true
98+
regBankSelected: true
99+
tracksRegLiveness: true
100+
body: |
101+
bb.1.entry:
102+
liveins: $a0, $a1, $a2
103+
104+
; MIPS32FP32-LABEL: name: select_float
105+
; MIPS32FP32: liveins: $a0, $a1, $a2
106+
; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
107+
; MIPS32FP32: [[MTC1_:%[0-9]+]]:fgr32 = MTC1 $a1
108+
; MIPS32FP32: [[MTC1_1:%[0-9]+]]:fgr32 = MTC1 $a2
109+
; MIPS32FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
110+
; MIPS32FP32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
111+
; MIPS32FP32: [[MOVN_I_S:%[0-9]+]]:fgr32 = MOVN_I_S [[MTC1_]], [[AND]], [[MTC1_1]]
112+
; MIPS32FP32: $f0 = COPY [[MOVN_I_S]]
113+
; MIPS32FP32: RetRA implicit $f0
114+
; MIPS32FP64-LABEL: name: select_float
115+
; MIPS32FP64: liveins: $a0, $a1, $a2
116+
; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
117+
; MIPS32FP64: [[MTC1_:%[0-9]+]]:fgr32 = MTC1 $a1
118+
; MIPS32FP64: [[MTC1_1:%[0-9]+]]:fgr32 = MTC1 $a2
119+
; MIPS32FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
120+
; MIPS32FP64: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
121+
; MIPS32FP64: [[MOVN_I_S:%[0-9]+]]:fgr32 = MOVN_I_S [[MTC1_]], [[AND]], [[MTC1_1]]
122+
; MIPS32FP64: $f0 = COPY [[MOVN_I_S]]
123+
; MIPS32FP64: RetRA implicit $f0
124+
%3:gprb(s32) = COPY $a0
125+
%1:fgr32(s32) = MTC1 $a1
126+
%2:fgr32(s32) = MTC1 $a2
127+
%6:gprb(s32) = G_CONSTANT i32 1
128+
%7:gprb(s32) = COPY %3(s32)
129+
%5:gprb(s32) = G_AND %7, %6
130+
%4:fprb(s32) = G_SELECT %5(s32), %1, %2
131+
$f0 = COPY %4(s32)
132+
RetRA implicit $f0
133+
134+
...
135+
---
136+
name: select_double
137+
alignment: 2
138+
legalized: true
139+
regBankSelected: true
140+
tracksRegLiveness: true
141+
fixedStack:
142+
- { id: 0, offset: 16, size: 4, alignment: 8, isImmutable: true }
143+
body: |
144+
bb.1.entry:
145+
liveins: $d6, $d7
146+
147+
; MIPS32FP32-LABEL: name: select_double
148+
; MIPS32FP32: liveins: $d6, $d7
149+
; MIPS32FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
150+
; MIPS32FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
151+
; MIPS32FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
152+
; MIPS32FP32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8)
153+
; MIPS32FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
154+
; MIPS32FP32: [[AND:%[0-9]+]]:gpr32 = AND [[LW]], [[ORi]]
155+
; MIPS32FP32: [[MOVN_I_D32_:%[0-9]+]]:afgr64 = MOVN_I_D32 [[COPY]], [[AND]], [[COPY1]]
156+
; MIPS32FP32: $d0 = COPY [[MOVN_I_D32_]]
157+
; MIPS32FP32: RetRA implicit $d0
158+
; MIPS32FP64-LABEL: name: select_double
159+
; MIPS32FP64: liveins: $d6, $d7
160+
; MIPS32FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
161+
; MIPS32FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
162+
; MIPS32FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
163+
; MIPS32FP64: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8)
164+
; MIPS32FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
165+
; MIPS32FP64: [[AND:%[0-9]+]]:gpr32 = AND [[LW]], [[ORi]]
166+
; MIPS32FP64: [[MOVN_I_D64_:%[0-9]+]]:fgr64 = MOVN_I_D64 [[COPY]], [[AND]], [[COPY1]]
167+
; MIPS32FP64: $d0 = COPY [[MOVN_I_D64_]]
168+
; MIPS32FP64: RetRA implicit $d0
169+
%0:fprb(s64) = COPY $d6
170+
%1:fprb(s64) = COPY $d7
171+
%4:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
172+
%3:gprb(s32) = G_LOAD %4(p0) :: (load 4 from %fixed-stack.0, align 8)
173+
%7:gprb(s32) = G_CONSTANT i32 1
174+
%8:gprb(s32) = COPY %3(s32)
175+
%6:gprb(s32) = G_AND %8, %7
176+
%5:fprb(s64) = G_SELECT %6(s32), %0, %1
177+
$d0 = COPY %5(s64)
178+
RetRA implicit $d0
179+
180+
...

‎llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir

Lines changed: 110 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,9 @@
77
define void @select_i32() {entry: ret void}
88
define void @select_ptr() {entry: ret void}
99
define void @select_with_negation() {entry: ret void}
10+
define void @select_i64() {entry: ret void}
11+
define void @select_float() {entry: ret void}
12+
define void @select_double() {entry: ret void}
1013

1114
...
1215
---
@@ -170,3 +173,110 @@ body: |
170173
RetRA implicit $v0
171174
172175
...
176+
---
177+
name: select_i64
178+
alignment: 2
179+
tracksRegLiveness: true
180+
fixedStack:
181+
- { id: 0, offset: 20, size: 4, alignment: 4, isImmutable: true }
182+
- { id: 1, offset: 16, size: 4, alignment: 8, isImmutable: true }
183+
body: |
184+
bb.1.entry:
185+
liveins: $a0, $a2, $a3
186+
187+
; MIPS32-LABEL: name: select_i64
188+
; MIPS32: liveins: $a0, $a2, $a3
189+
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
190+
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
191+
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
192+
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
193+
; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
194+
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 8)
195+
; MIPS32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
196+
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load 4 from %fixed-stack.1)
197+
; MIPS32: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
198+
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
199+
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
200+
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
201+
; MIPS32: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[MV]], [[MV1]]
202+
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SELECT]](s64)
203+
; MIPS32: $v0 = COPY [[UV]](s32)
204+
; MIPS32: $v1 = COPY [[UV1]](s32)
205+
; MIPS32: RetRA implicit $v0, implicit $v1
206+
%3:_(s32) = COPY $a0
207+
%0:_(s1) = G_TRUNC %3(s32)
208+
%4:_(s32) = COPY $a2
209+
%5:_(s32) = COPY $a3
210+
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
211+
%8:_(p0) = G_FRAME_INDEX %fixed-stack.1
212+
%6:_(s32) = G_LOAD %8(p0) :: (load 4 from %fixed-stack.1, align 8)
213+
%9:_(p0) = G_FRAME_INDEX %fixed-stack.0
214+
%7:_(s32) = G_LOAD %9(p0) :: (load 4 from %fixed-stack.0)
215+
%2:_(s64) = G_MERGE_VALUES %6(s32), %7(s32)
216+
%10:_(s64) = G_SELECT %0(s1), %1, %2
217+
%11:_(s32), %12:_(s32) = G_UNMERGE_VALUES %10(s64)
218+
$v0 = COPY %11(s32)
219+
$v1 = COPY %12(s32)
220+
RetRA implicit $v0, implicit $v1
221+
222+
...
223+
---
224+
name: select_float
225+
alignment: 2
226+
tracksRegLiveness: true
227+
body: |
228+
bb.1.entry:
229+
liveins: $a0, $a1, $a2
230+
231+
; MIPS32-LABEL: name: select_float
232+
; MIPS32: liveins: $a0, $a1, $a2
233+
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
234+
; MIPS32: [[MTC1_:%[0-9]+]]:fgr32(s32) = MTC1 $a1
235+
; MIPS32: [[MTC1_1:%[0-9]+]]:fgr32(s32) = MTC1 $a2
236+
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
237+
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
238+
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
239+
; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[MTC1_]], [[MTC1_1]]
240+
; MIPS32: $f0 = COPY [[SELECT]](s32)
241+
; MIPS32: RetRA implicit $f0
242+
%3:_(s32) = COPY $a0
243+
%0:_(s1) = G_TRUNC %3(s32)
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%1:fgr32(s32) = MTC1 $a1
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%2:fgr32(s32) = MTC1 $a2
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%4:_(s32) = G_SELECT %0(s1), %1, %2
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$f0 = COPY %4(s32)
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RetRA implicit $f0
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...
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---
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name: select_double
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alignment: 2
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tracksRegLiveness: true
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fixedStack:
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- { id: 0, offset: 16, size: 4, alignment: 8, isImmutable: true }
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body: |
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bb.1.entry:
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liveins: $d6, $d7
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; MIPS32-LABEL: name: select_double
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; MIPS32: liveins: $d6, $d7
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; MIPS32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
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; MIPS32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
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; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
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; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 8)
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
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; MIPS32: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]]
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; MIPS32: $d0 = COPY [[SELECT]](s64)
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; MIPS32: RetRA implicit $d0
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%0:_(s64) = COPY $d6
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%1:_(s64) = COPY $d7
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%4:_(p0) = G_FRAME_INDEX %fixed-stack.0
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%3:_(s32) = G_LOAD %4(p0) :: (load 4 from %fixed-stack.0, align 8)
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%2:_(s1) = G_TRUNC %3(s32)
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%5:_(s64) = G_SELECT %2(s1), %0, %1
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$d0 = COPY %5(s64)
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RetRA implicit $d0
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...

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