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[RISCV] Prevent selecting a 0 VL to X0 for the segment load/store intrinsics.
Just like we do for isel patterns, we need to call selectVLOp to prevent 0 from being selected to X0 by the default isel. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D97021
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-5
lines changed

2 files changed

+276
-5
lines changed

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Lines changed: 15 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -201,7 +201,9 @@ void RISCVDAGToDAGISel::selectVLSEG(SDNode *Node, bool IsMasked,
201201
Operands.push_back(Node->getOperand(CurOp++)); // Stride.
202202
if (IsMasked)
203203
Operands.push_back(Node->getOperand(CurOp++)); // Mask.
204-
Operands.push_back(Node->getOperand(CurOp++)); // VL.
204+
SDValue VL;
205+
selectVLOp(Node->getOperand(CurOp++), VL);
206+
Operands.push_back(VL);
205207
Operands.push_back(SEW);
206208
Operands.push_back(Node->getOperand(0)); // Chain.
207209
const RISCV::VLSEGPseudo *P =
@@ -240,7 +242,9 @@ void RISCVDAGToDAGISel::selectVLSEGFF(SDNode *Node, bool IsMasked) {
240242
Operands.push_back(Node->getOperand(CurOp++)); // Base pointer.
241243
if (IsMasked)
242244
Operands.push_back(Node->getOperand(CurOp++)); // Mask.
243-
Operands.push_back(Node->getOperand(CurOp++)); // VL.
245+
SDValue VL;
246+
selectVLOp(Node->getOperand(CurOp++), VL);
247+
Operands.push_back(VL);
244248
Operands.push_back(SEW);
245249
Operands.push_back(Node->getOperand(0)); // Chain.
246250
const RISCV::VLSEGPseudo *P =
@@ -285,7 +289,9 @@ void RISCVDAGToDAGISel::selectVLXSEG(SDNode *Node, bool IsMasked,
285289
MVT IndexVT = Operands.back()->getSimpleValueType(0);
286290
if (IsMasked)
287291
Operands.push_back(Node->getOperand(CurOp++)); // Mask.
288-
Operands.push_back(Node->getOperand(CurOp++)); // VL.
292+
SDValue VL;
293+
selectVLOp(Node->getOperand(CurOp++), VL);
294+
Operands.push_back(VL);
289295
Operands.push_back(SEW);
290296
Operands.push_back(Node->getOperand(0)); // Chain.
291297

@@ -329,7 +335,9 @@ void RISCVDAGToDAGISel::selectVSSEG(SDNode *Node, bool IsMasked,
329335
Operands.push_back(Node->getOperand(CurOp++)); // Stride.
330336
if (IsMasked)
331337
Operands.push_back(Node->getOperand(CurOp++)); // Mask.
332-
Operands.push_back(Node->getOperand(CurOp++)); // VL.
338+
SDValue VL;
339+
selectVLOp(Node->getOperand(CurOp++), VL);
340+
Operands.push_back(VL);
333341
Operands.push_back(SEW);
334342
Operands.push_back(Node->getOperand(0)); // Chain.
335343
const RISCV::VSSEGPseudo *P = RISCV::getVSSEGPseudo(
@@ -360,7 +368,9 @@ void RISCVDAGToDAGISel::selectVSXSEG(SDNode *Node, bool IsMasked,
360368
MVT IndexVT = Operands.back()->getSimpleValueType(0);
361369
if (IsMasked)
362370
Operands.push_back(Node->getOperand(CurOp++)); // Mask.
363-
Operands.push_back(Node->getOperand(CurOp++)); // VL.
371+
SDValue VL;
372+
selectVLOp(Node->getOperand(CurOp++), VL);
373+
Operands.push_back(VL);
364374
Operands.push_back(SEW);
365375
Operands.push_back(Node->getOperand(0)); // Chain.
366376

‎llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll

Lines changed: 261 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,261 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \
3+
; RUN: -verify-machineinstrs < %s | FileCheck %s
4+
5+
; Make sure we don't select a 0 vl to X0 in the custom isel handlers we use
6+
; for these intrinsics.
7+
8+
declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.nxv16i16(i16* , i64)
9+
declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i64)
10+
11+
define <vscale x 16 x i16> @test_vlseg2_mask_nxv16i16(i16* %base, <vscale x 16 x i1> %mask) {
12+
; CHECK-LABEL: test_vlseg2_mask_nxv16i16:
13+
; CHECK: # %bb.0: # %entry
14+
; CHECK-NEXT: mv a1, zero
15+
; CHECK-NEXT: vsetvli a2, a1, e16,m4,ta,mu
16+
; CHECK-NEXT: vlseg2e16.v v4, (a0)
17+
; CHECK-NEXT: vmv4r.v v8, v4
18+
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
19+
; CHECK-NEXT: vlseg2e16.v v4, (a0), v0.t
20+
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
21+
; CHECK-NEXT: ret
22+
entry:
23+
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.nxv16i16(i16* %base, i64 0)
24+
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
25+
%2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.mask.nxv16i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 16 x i1> %mask, i64 0)
26+
%3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
27+
ret <vscale x 16 x i16> %3
28+
}
29+
30+
declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.nxv16i16(i16*, i64, i64)
31+
declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i64, <vscale x 16 x i1>, i64)
32+
33+
define <vscale x 16 x i16> @test_vlsseg2_mask_nxv16i16(i16* %base, i64 %offset, <vscale x 16 x i1> %mask) {
34+
; CHECK-LABEL: test_vlsseg2_mask_nxv16i16:
35+
; CHECK: # %bb.0: # %entry
36+
; CHECK-NEXT: mv a2, zero
37+
; CHECK-NEXT: vsetvli a3, a2, e16,m4,ta,mu
38+
; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1
39+
; CHECK-NEXT: vmv4r.v v8, v4
40+
; CHECK-NEXT: vsetvli a2, a2, e16,m4,tu,mu
41+
; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1, v0.t
42+
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
43+
; CHECK-NEXT: ret
44+
entry:
45+
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.nxv16i16(i16* %base, i64 %offset, i64 0)
46+
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
47+
%2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.mask.nxv16i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 0)
48+
%3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
49+
ret <vscale x 16 x i16> %3
50+
}
51+
declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vloxseg2.nxv16i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
52+
declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vloxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
53+
54+
define <vscale x 16 x i16> @test_vloxseg2_mask_nxv16i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask) {
55+
; CHECK-LABEL: test_vloxseg2_mask_nxv16i16_nxv16i16:
56+
; CHECK: # %bb.0: # %entry
57+
; CHECK-NEXT: mv a1, zero
58+
; CHECK-NEXT: vsetvli a2, a1, e16,m4,ta,mu
59+
; CHECK-NEXT: vloxseg2ei16.v v12, (a0), v8
60+
; CHECK-NEXT: vmv4r.v v16, v12
61+
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
62+
; CHECK-NEXT: vloxseg2ei16.v v12, (a0), v8, v0.t
63+
; CHECK-NEXT: vmv4r.v v8, v16
64+
; CHECK-NEXT: ret
65+
entry:
66+
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vloxseg2.nxv16i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 0)
67+
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
68+
%2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vloxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 0)
69+
%3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
70+
ret <vscale x 16 x i16> %3
71+
}
72+
73+
declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
74+
declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
75+
76+
define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask) {
77+
; CHECK-LABEL: test_vluxseg2_mask_nxv16i16_nxv16i16:
78+
; CHECK: # %bb.0: # %entry
79+
; CHECK-NEXT: mv a1, zero
80+
; CHECK-NEXT: vsetvli a2, a1, e16,m4,ta,mu
81+
; CHECK-NEXT: vluxseg2ei16.v v12, (a0), v8
82+
; CHECK-NEXT: vmv4r.v v16, v12
83+
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
84+
; CHECK-NEXT: vluxseg2ei16.v v12, (a0), v8, v0.t
85+
; CHECK-NEXT: vmv4r.v v8, v16
86+
; CHECK-NEXT: ret
87+
entry:
88+
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 0)
89+
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
90+
%2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 0)
91+
%3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
92+
ret <vscale x 16 x i16> %3
93+
}
94+
95+
declare {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* , i64)
96+
declare {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i64)
97+
98+
define <vscale x 16 x i16> @test_vlseg2ff_nxv16i16(i16* %base, i64* %outvl) {
99+
; CHECK-LABEL: test_vlseg2ff_nxv16i16:
100+
; CHECK: # %bb.0: # %entry
101+
; CHECK-NEXT: mv a2, zero
102+
; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu
103+
; CHECK-NEXT: vlseg2e16ff.v v4, (a0)
104+
; CHECK-NEXT: csrr a0, vl
105+
; CHECK-NEXT: sd a0, 0(a1)
106+
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
107+
; CHECK-NEXT: ret
108+
entry:
109+
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* %base, i64 0)
110+
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 1
111+
%2 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 2
112+
store i64 %2, i64* %outvl
113+
ret <vscale x 16 x i16> %1
114+
}
115+
116+
define <vscale x 16 x i16> @test_vlseg2ff_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64* %outvl) {
117+
; CHECK-LABEL: test_vlseg2ff_mask_nxv16i16:
118+
; CHECK: # %bb.0: # %entry
119+
; CHECK-NEXT: vmv4r.v v4, v8
120+
; CHECK-NEXT: mv a2, zero
121+
; CHECK-NEXT: vsetvli a2, a2, e16,m4,tu,mu
122+
; CHECK-NEXT: vlseg2e16ff.v v4, (a0), v0.t
123+
; CHECK-NEXT: csrr a0, vl
124+
; CHECK-NEXT: sd a0, 0(a1)
125+
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
126+
; CHECK-NEXT: ret
127+
entry:
128+
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 0)
129+
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 1
130+
%2 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 2
131+
store i64 %2, i64* %outvl
132+
ret <vscale x 16 x i16> %1
133+
}
134+
135+
declare void @llvm.riscv.vsseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16* , i64)
136+
declare void @llvm.riscv.vsseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i64)
137+
138+
define void @test_vsseg2_nxv16i16(<vscale x 16 x i16> %val, i16* %base) {
139+
; CHECK-LABEL: test_vsseg2_nxv16i16:
140+
; CHECK: # %bb.0: # %entry
141+
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
142+
; CHECK-NEXT: vmv4r.v v12, v8
143+
; CHECK-NEXT: mv a1, zero
144+
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
145+
; CHECK-NEXT: vsseg2e16.v v8, (a0)
146+
; CHECK-NEXT: ret
147+
entry:
148+
tail call void @llvm.riscv.vsseg2.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, i64 0)
149+
ret void
150+
}
151+
152+
define void @test_vsseg2_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask) {
153+
; CHECK-LABEL: test_vsseg2_mask_nxv16i16:
154+
; CHECK: # %bb.0: # %entry
155+
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
156+
; CHECK-NEXT: vmv4r.v v12, v8
157+
; CHECK-NEXT: mv a1, zero
158+
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
159+
; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t
160+
; CHECK-NEXT: ret
161+
entry:
162+
tail call void @llvm.riscv.vsseg2.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 0)
163+
ret void
164+
}
165+
166+
declare void @llvm.riscv.vssseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i64, i64)
167+
declare void @llvm.riscv.vssseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i64, <vscale x 16 x i1>, i64)
168+
169+
define void @test_vssseg2_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i64 %offset) {
170+
; CHECK-LABEL: test_vssseg2_nxv16i16:
171+
; CHECK: # %bb.0: # %entry
172+
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
173+
; CHECK-NEXT: vmv4r.v v12, v8
174+
; CHECK-NEXT: mv a2, zero
175+
; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu
176+
; CHECK-NEXT: vssseg2e16.v v8, (a0), a1
177+
; CHECK-NEXT: ret
178+
entry:
179+
tail call void @llvm.riscv.vssseg2.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, i64 %offset, i64 0)
180+
ret void
181+
}
182+
183+
define void @test_vssseg2_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i64 %offset, <vscale x 16 x i1> %mask) {
184+
; CHECK-LABEL: test_vssseg2_mask_nxv16i16:
185+
; CHECK: # %bb.0: # %entry
186+
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
187+
; CHECK-NEXT: vmv4r.v v12, v8
188+
; CHECK-NEXT: mv a2, zero
189+
; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu
190+
; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t
191+
; CHECK-NEXT: ret
192+
entry:
193+
tail call void @llvm.riscv.vssseg2.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 0)
194+
ret void
195+
}
196+
197+
declare void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i16>, i64)
198+
declare void @llvm.riscv.vsoxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
199+
200+
define void @test_vsoxseg2_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index) {
201+
; CHECK-LABEL: test_vsoxseg2_nxv16i16_nxv16i16:
202+
; CHECK: # %bb.0: # %entry
203+
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
204+
; CHECK-NEXT: vmv4r.v v28, v12
205+
; CHECK-NEXT: vmv4r.v v12, v8
206+
; CHECK-NEXT: mv a1, zero
207+
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
208+
; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v28
209+
; CHECK-NEXT: ret
210+
entry:
211+
tail call void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 0)
212+
ret void
213+
}
214+
215+
define void @test_vsoxseg2_mask_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask) {
216+
; CHECK-LABEL: test_vsoxseg2_mask_nxv16i16_nxv16i16:
217+
; CHECK: # %bb.0: # %entry
218+
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
219+
; CHECK-NEXT: vmv4r.v v28, v12
220+
; CHECK-NEXT: vmv4r.v v12, v8
221+
; CHECK-NEXT: mv a1, zero
222+
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
223+
; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v28, v0.t
224+
; CHECK-NEXT: ret
225+
entry:
226+
tail call void @llvm.riscv.vsoxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 0)
227+
ret void
228+
}
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declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i16>, i64)
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declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
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define void @test_vsuxseg2_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index) {
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; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv16i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
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; CHECK-NEXT: vmv4r.v v28, v12
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; CHECK-NEXT: vmv4r.v v12, v8
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; CHECK-NEXT: mv a1, zero
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; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
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; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28
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; CHECK-NEXT: ret
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entry:
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tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 0)
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ret void
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}
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define void @test_vsuxseg2_mask_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask) {
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; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv16i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
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; CHECK-NEXT: vmv4r.v v28, v12
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; CHECK-NEXT: vmv4r.v v12, v8
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; CHECK-NEXT: mv a1, zero
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; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
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; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28, v0.t
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; CHECK-NEXT: ret
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entry:
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tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 0)
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ret void
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}

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