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[LV] Add option to tune the cost model, NFC
For Neon, the default nonconst stride cost is conservative, and it is a local variable, which is not convenience to to tune the loop vectorize. So I try to use a option, which is similar to SVEGatherOverhead brought in D115143. Fix llvm#63082. Reviewed By: dmgreen, fhahn Differential Revision: https://reviews.llvm.org/D152253
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‎llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

Lines changed: 5 additions & 1 deletion
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@@ -42,6 +42,10 @@ static cl::opt<unsigned> SVEScatterOverhead("sve-scatter-overhead",
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static cl::opt<unsigned> SVETailFoldInsnThreshold("sve-tail-folding-insn-threshold",
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cl::init(15), cl::Hidden);
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static cl::opt<unsigned>
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NeonNonConstStrideOverhead("neon-nonconst-stride-overhead", cl::init(10),
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cl::Hidden);
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namespace {
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class TailFoldingOption {
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// These bitfields will only ever be set to something non-zero in operator=,
@@ -2577,7 +2581,7 @@ InstructionCost AArch64TTIImpl::getAddressComputationCost(Type *Ty,
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// likely result in more instructions compared to scalar code where the
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// computation can more often be merged into the index mode. The resulting
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// extra micro-ops can significantly decrease throughput.
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unsigned NumVectorInstToHideOverhead = 10;
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unsigned NumVectorInstToHideOverhead = NeonNonConstStrideOverhead;
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int MaxMergeDistance = 64;
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if (Ty->isVectorTy() && SE &&

‎llvm/test/Transforms/LoopVectorize/AArch64/neon-gather-cost.ll

Lines changed: 84 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,84 @@
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; RUN: opt -passes=loop-vectorize -mtriple=arm64-apple-ios -S -mcpu=cyclone -enable-interleaved-mem-accesses=false -neon-nonconst-stride-overhead=5 < %s | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"
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@kernel = global [512 x float] zeroinitializer, align 16
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@kernel2 = global [512 x float] zeroinitializer, align 16
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@kernel3 = global [512 x float] zeroinitializer, align 16
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@kernel4 = global [512 x float] zeroinitializer, align 16
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@src_data = global [1536 x float] zeroinitializer, align 16
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@r_ = global i8 0, align 1
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@g_ = global i8 0, align 1
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@b_ = global i8 0, align 1
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; vectorize loop when we lower the cost of gather load
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; Make sure we vectorize it, VF = 4
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; CHECK: <4 x float>
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define void @_Z4testmm(i64 %size, i64 %offset) {
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entry:
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%cmp53 = icmp eq i64 %size, 0
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br i1 %cmp53, label %for.end, label %for.body.lr.ph
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for.body.lr.ph:
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br label %for.body
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for.body:
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%r.057 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add10, %for.body ]
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%g.056 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add20, %for.body ]
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%v.055 = phi i64 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
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%b.054 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add30, %for.body ]
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%add = add i64 %v.055, %offset
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%mul = mul i64 %add, 3
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%arrayidx = getelementptr inbounds [1536 x float], ptr @src_data, i64 0, i64 %mul
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%0 = load float, ptr %arrayidx, align 4
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%arrayidx2 = getelementptr inbounds [512 x float], ptr @kernel, i64 0, i64 %v.055
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%1 = load float, ptr %arrayidx2, align 4
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%mul3 = fmul fast float %0, %1
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%arrayidx4 = getelementptr inbounds [512 x float], ptr @kernel2, i64 0, i64 %v.055
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%2 = load float, ptr %arrayidx4, align 4
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%mul5 = fmul fast float %mul3, %2
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%arrayidx6 = getelementptr inbounds [512 x float], ptr @kernel3, i64 0, i64 %v.055
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%3 = load float, ptr %arrayidx6, align 4
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%mul7 = fmul fast float %mul5, %3
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%arrayidx8 = getelementptr inbounds [512 x float], ptr @kernel4, i64 0, i64 %v.055
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%4 = load float, ptr %arrayidx8, align 4
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%mul9 = fmul fast float %mul7, %4
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%add10 = fadd fast float %r.057, %mul9
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%arrayidx.sum = add i64 %mul, 1
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%arrayidx11 = getelementptr inbounds [1536 x float], ptr @src_data, i64 0, i64 %arrayidx.sum
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%5 = load float, ptr %arrayidx11, align 4
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%mul13 = fmul fast float %1, %5
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%mul15 = fmul fast float %2, %mul13
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%mul17 = fmul fast float %3, %mul15
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%mul19 = fmul fast float %4, %mul17
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%add20 = fadd fast float %g.056, %mul19
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%arrayidx.sum52 = add i64 %mul, 2
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%arrayidx21 = getelementptr inbounds [1536 x float], ptr @src_data, i64 0, i64 %arrayidx.sum52
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%6 = load float, ptr %arrayidx21, align 4
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%mul23 = fmul fast float %1, %6
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%mul25 = fmul fast float %2, %mul23
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%mul27 = fmul fast float %3, %mul25
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%mul29 = fmul fast float %4, %mul27
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%add30 = fadd fast float %b.054, %mul29
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%inc = add i64 %v.055, 1
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%exitcond = icmp ne i64 %inc, %size
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br i1 %exitcond, label %for.body, label %for.cond.for.end_crit_edge
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for.cond.for.end_crit_edge:
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%add30.lcssa = phi float [ %add30, %for.body ]
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%add20.lcssa = phi float [ %add20, %for.body ]
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%add10.lcssa = phi float [ %add10, %for.body ]
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%phitmp = fptoui float %add10.lcssa to i8
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%phitmp60 = fptoui float %add20.lcssa to i8
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%phitmp61 = fptoui float %add30.lcssa to i8
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br label %for.end
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for.end:
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%r.0.lcssa = phi i8 [ %phitmp, %for.cond.for.end_crit_edge ], [ 0, %entry ]
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%g.0.lcssa = phi i8 [ %phitmp60, %for.cond.for.end_crit_edge ], [ 0, %entry ]
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%b.0.lcssa = phi i8 [ %phitmp61, %for.cond.for.end_crit_edge ], [ 0, %entry ]
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store i8 %r.0.lcssa, ptr @r_, align 1
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store i8 %g.0.lcssa, ptr @g_, align 1
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store i8 %b.0.lcssa, ptr @b_, align 1
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ret void
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}

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