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[LegalizeIntegerTypes] Improve ExpandIntRes_SADDSUBO codegen on targets without SADDO/SSUBO.
This code creates 3 setccs that need to be expanded. It was creating a sign bit test as setge X, 0 which is non-canonical. Canonical would be setgt X, -1. This misses the special case in IntegerExpandSetCCOperands for sign bit tests that assumes canonical form. If we don't hit this special case we end up with a multipart setcc instead of just checking the sign of the high part. To fix this I've reversed the polarity of all of the setccs to setlt X, 0 which is canonical. The rest of the logic should still work. This seems to produce better code on RISCV which lacks a setgt instruction. This probably still isn't the best code sequence we could use here. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97181
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13 files changed

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‎llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -3661,9 +3661,9 @@ void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
36613661

36623662
// Compute the overflow.
36633663
//
3664-
// LHSSign -> LHS >= 0
3665-
// RHSSign -> RHS >= 0
3666-
// SumSign -> Sum >= 0
3664+
// LHSSign -> LHS < 0
3665+
// RHSSign -> RHS < 0
3666+
// SumSign -> Sum < 0
36673667
//
36683668
// Add:
36693669
// Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
@@ -3673,13 +3673,13 @@ void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
36733673
EVT OType = Node->getValueType(1);
36743674
SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
36753675

3676-
SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3677-
SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3676+
SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETLT);
3677+
SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETLT);
36783678
SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
36793679
Node->getOpcode() == ISD::SADDO ?
36803680
ISD::SETEQ : ISD::SETNE);
36813681

3682-
SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3682+
SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETLT);
36833683
SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
36843684

36853685
Ovf = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);

‎llvm/test/CodeGen/AArch64/sadd_sat_vec.ll

Lines changed: 11 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -367,39 +367,33 @@ define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
367367
; CHECK-LABEL: v2i128:
368368
; CHECK: // %bb.0:
369369
; CHECK-NEXT: cmp x7, #0 // =0
370-
; CHECK-NEXT: cset w9, ge
371-
; CHECK-NEXT: csinc w9, w9, wzr, ne
370+
; CHECK-NEXT: cset w9, lt
372371
; CHECK-NEXT: cmp x3, #0 // =0
373-
; CHECK-NEXT: cset w10, ge
374-
; CHECK-NEXT: csinc w10, w10, wzr, ne
372+
; CHECK-NEXT: cset w10, lt
375373
; CHECK-NEXT: cmp w10, w9
376374
; CHECK-NEXT: cset w9, eq
377375
; CHECK-NEXT: adds x11, x2, x6
378376
; CHECK-NEXT: adcs x12, x3, x7
379377
; CHECK-NEXT: cmp x12, #0 // =0
380-
; CHECK-NEXT: cset w13, ge
381378
; CHECK-NEXT: mov x8, #9223372036854775807
382-
; CHECK-NEXT: csinc w13, w13, wzr, ne
379+
; CHECK-NEXT: cset w15, lt
383380
; CHECK-NEXT: cinv x14, x8, ge
384-
; CHECK-NEXT: cmp w10, w13
385-
; CHECK-NEXT: cset w13, ne
386-
; CHECK-NEXT: asr x10, x12, #63
387-
; CHECK-NEXT: tst w9, w13
381+
; CHECK-NEXT: cmp w10, w15
382+
; CHECK-NEXT: cset w10, ne
383+
; CHECK-NEXT: asr x13, x12, #63
384+
; CHECK-NEXT: tst w9, w10
385+
; CHECK-NEXT: csel x2, x13, x11, ne
388386
; CHECK-NEXT: csel x3, x14, x12, ne
389-
; CHECK-NEXT: csel x2, x10, x11, ne
390387
; CHECK-NEXT: cmp x5, #0 // =0
391-
; CHECK-NEXT: cset w9, ge
392-
; CHECK-NEXT: csinc w9, w9, wzr, ne
388+
; CHECK-NEXT: cset w9, lt
393389
; CHECK-NEXT: cmp x1, #0 // =0
394-
; CHECK-NEXT: cset w10, ge
395-
; CHECK-NEXT: csinc w10, w10, wzr, ne
390+
; CHECK-NEXT: cset w10, lt
396391
; CHECK-NEXT: cmp w10, w9
397392
; CHECK-NEXT: cset w9, eq
398393
; CHECK-NEXT: adds x11, x0, x4
399394
; CHECK-NEXT: adcs x12, x1, x5
400395
; CHECK-NEXT: cmp x12, #0 // =0
401-
; CHECK-NEXT: cset w13, ge
402-
; CHECK-NEXT: csinc w13, w13, wzr, ne
396+
; CHECK-NEXT: cset w13, lt
403397
; CHECK-NEXT: cinv x8, x8, ge
404398
; CHECK-NEXT: cmp w10, w13
405399
; CHECK-NEXT: cset w10, ne

‎llvm/test/CodeGen/AArch64/ssub_sat_vec.ll

Lines changed: 11 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -370,39 +370,33 @@ define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
370370
; CHECK-LABEL: v2i128:
371371
; CHECK: // %bb.0:
372372
; CHECK-NEXT: cmp x7, #0 // =0
373-
; CHECK-NEXT: cset w9, ge
374-
; CHECK-NEXT: csinc w9, w9, wzr, ne
373+
; CHECK-NEXT: cset w9, lt
375374
; CHECK-NEXT: cmp x3, #0 // =0
376-
; CHECK-NEXT: cset w10, ge
377-
; CHECK-NEXT: csinc w10, w10, wzr, ne
375+
; CHECK-NEXT: cset w10, lt
378376
; CHECK-NEXT: cmp w10, w9
379377
; CHECK-NEXT: cset w9, ne
380378
; CHECK-NEXT: subs x11, x2, x6
381379
; CHECK-NEXT: sbcs x12, x3, x7
382380
; CHECK-NEXT: cmp x12, #0 // =0
383-
; CHECK-NEXT: cset w13, ge
384381
; CHECK-NEXT: mov x8, #9223372036854775807
385-
; CHECK-NEXT: csinc w13, w13, wzr, ne
382+
; CHECK-NEXT: cset w15, lt
386383
; CHECK-NEXT: cinv x14, x8, ge
387-
; CHECK-NEXT: cmp w10, w13
388-
; CHECK-NEXT: cset w13, ne
389-
; CHECK-NEXT: asr x10, x12, #63
390-
; CHECK-NEXT: tst w9, w13
384+
; CHECK-NEXT: cmp w10, w15
385+
; CHECK-NEXT: cset w10, ne
386+
; CHECK-NEXT: asr x13, x12, #63
387+
; CHECK-NEXT: tst w9, w10
388+
; CHECK-NEXT: csel x2, x13, x11, ne
391389
; CHECK-NEXT: csel x3, x14, x12, ne
392-
; CHECK-NEXT: csel x2, x10, x11, ne
393390
; CHECK-NEXT: cmp x5, #0 // =0
394-
; CHECK-NEXT: cset w9, ge
395-
; CHECK-NEXT: csinc w9, w9, wzr, ne
391+
; CHECK-NEXT: cset w9, lt
396392
; CHECK-NEXT: cmp x1, #0 // =0
397-
; CHECK-NEXT: cset w10, ge
398-
; CHECK-NEXT: csinc w10, w10, wzr, ne
393+
; CHECK-NEXT: cset w10, lt
399394
; CHECK-NEXT: cmp w10, w9
400395
; CHECK-NEXT: cset w9, ne
401396
; CHECK-NEXT: subs x11, x0, x4
402397
; CHECK-NEXT: sbcs x12, x1, x5
403398
; CHECK-NEXT: cmp x12, #0 // =0
404-
; CHECK-NEXT: cset w13, ge
405-
; CHECK-NEXT: csinc w13, w13, wzr, ne
399+
; CHECK-NEXT: cset w13, lt
406400
; CHECK-NEXT: cinv x8, x8, ge
407401
; CHECK-NEXT: cmp w10, w13
408402
; CHECK-NEXT: cset w10, ne

‎llvm/test/CodeGen/ARM/sadd_sat.ll

Lines changed: 20 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -104,13 +104,13 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
104104
; CHECK-T1-NEXT: movs r0, #0
105105
; CHECK-T1-NEXT: cmp r3, #0
106106
; CHECK-T1-NEXT: mov r5, r4
107-
; CHECK-T1-NEXT: bge .LBB1_2
107+
; CHECK-T1-NEXT: bmi .LBB1_2
108108
; CHECK-T1-NEXT: @ %bb.1:
109109
; CHECK-T1-NEXT: mov r5, r0
110110
; CHECK-T1-NEXT: .LBB1_2:
111111
; CHECK-T1-NEXT: cmp r1, #0
112112
; CHECK-T1-NEXT: mov r7, r4
113-
; CHECK-T1-NEXT: bge .LBB1_4
113+
; CHECK-T1-NEXT: bmi .LBB1_4
114114
; CHECK-T1-NEXT: @ %bb.3:
115115
; CHECK-T1-NEXT: mov r7, r0
116116
; CHECK-T1-NEXT: .LBB1_4:
@@ -120,9 +120,8 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
120120
; CHECK-T1-NEXT: ldr r6, [sp] @ 4-byte Reload
121121
; CHECK-T1-NEXT: adds r6, r2, r6
122122
; CHECK-T1-NEXT: adcs r1, r3
123-
; CHECK-T1-NEXT: cmp r1, #0
124123
; CHECK-T1-NEXT: mov r2, r4
125-
; CHECK-T1-NEXT: bge .LBB1_6
124+
; CHECK-T1-NEXT: bmi .LBB1_6
126125
; CHECK-T1-NEXT: @ %bb.5:
127126
; CHECK-T1-NEXT: mov r2, r0
128127
; CHECK-T1-NEXT: .LBB1_6:
@@ -161,23 +160,22 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
161160
; CHECK-T2: @ %bb.0:
162161
; CHECK-T2-NEXT: .save {r7, lr}
163162
; CHECK-T2-NEXT: push {r7, lr}
164-
; CHECK-T2-NEXT: cmp.w r1, #-1
163+
; CHECK-T2-NEXT: cmp r1, #0
165164
; CHECK-T2-NEXT: mov.w lr, #0
166-
; CHECK-T2-NEXT: it gt
167-
; CHECK-T2-NEXT: movgt.w lr, #1
165+
; CHECK-T2-NEXT: it mi
166+
; CHECK-T2-NEXT: movmi.w lr, #1
168167
; CHECK-T2-NEXT: adds r0, r0, r2
169-
; CHECK-T2-NEXT: adc.w r2, r1, r3
170-
; CHECK-T2-NEXT: movs r1, #0
171-
; CHECK-T2-NEXT: cmp.w r2, #-1
172-
; CHECK-T2-NEXT: it gt
173-
; CHECK-T2-NEXT: movgt r1, #1
174-
; CHECK-T2-NEXT: subs.w r1, lr, r1
168+
; CHECK-T2-NEXT: adcs.w r2, r1, r3
169+
; CHECK-T2-NEXT: mov.w r1, #0
170+
; CHECK-T2-NEXT: it mi
171+
; CHECK-T2-NEXT: movmi r1, #1
175172
; CHECK-T2-NEXT: mov.w r12, #0
173+
; CHECK-T2-NEXT: subs.w r1, lr, r1
176174
; CHECK-T2-NEXT: it ne
177175
; CHECK-T2-NEXT: movne r1, #1
178-
; CHECK-T2-NEXT: cmp.w r3, #-1
179-
; CHECK-T2-NEXT: it gt
180-
; CHECK-T2-NEXT: movgt.w r12, #1
176+
; CHECK-T2-NEXT: cmp r3, #0
177+
; CHECK-T2-NEXT: it mi
178+
; CHECK-T2-NEXT: movmi.w r12, #1
181179
; CHECK-T2-NEXT: sub.w r3, lr, r12
182180
; CHECK-T2-NEXT: clz r3, r3
183181
; CHECK-T2-NEXT: lsrs r3, r3, #5
@@ -197,19 +195,18 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
197195
; CHECK-ARM: @ %bb.0:
198196
; CHECK-ARM-NEXT: .save {r11, lr}
199197
; CHECK-ARM-NEXT: push {r11, lr}
200-
; CHECK-ARM-NEXT: cmn r1, #1
198+
; CHECK-ARM-NEXT: cmp r1, #0
201199
; CHECK-ARM-NEXT: mov lr, #0
202-
; CHECK-ARM-NEXT: movgt lr, #1
200+
; CHECK-ARM-NEXT: movmi lr, #1
203201
; CHECK-ARM-NEXT: adds r0, r0, r2
204-
; CHECK-ARM-NEXT: adc r2, r1, r3
202+
; CHECK-ARM-NEXT: adcs r2, r1, r3
205203
; CHECK-ARM-NEXT: mov r1, #0
206-
; CHECK-ARM-NEXT: cmn r2, #1
204+
; CHECK-ARM-NEXT: movmi r1, #1
207205
; CHECK-ARM-NEXT: mov r12, #0
208-
; CHECK-ARM-NEXT: movgt r1, #1
209206
; CHECK-ARM-NEXT: subs r1, lr, r1
210207
; CHECK-ARM-NEXT: movne r1, #1
211-
; CHECK-ARM-NEXT: cmn r3, #1
212-
; CHECK-ARM-NEXT: movgt r12, #1
208+
; CHECK-ARM-NEXT: cmp r3, #0
209+
; CHECK-ARM-NEXT: movmi r12, #1
213210
; CHECK-ARM-NEXT: sub r3, lr, r12
214211
; CHECK-ARM-NEXT: clz r3, r3
215212
; CHECK-ARM-NEXT: lsr r3, r3, #5

‎llvm/test/CodeGen/ARM/sadd_sat_plus.ll

Lines changed: 19 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -87,13 +87,13 @@ define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
8787
; CHECK-T1-NEXT: movs r4, #0
8888
; CHECK-T1-NEXT: cmp r5, #0
8989
; CHECK-T1-NEXT: mov r3, r2
90-
; CHECK-T1-NEXT: bge .LBB1_2
90+
; CHECK-T1-NEXT: bmi .LBB1_2
9191
; CHECK-T1-NEXT: @ %bb.1:
9292
; CHECK-T1-NEXT: mov r3, r4
9393
; CHECK-T1-NEXT: .LBB1_2:
9494
; CHECK-T1-NEXT: cmp r1, #0
9595
; CHECK-T1-NEXT: mov r6, r2
96-
; CHECK-T1-NEXT: bge .LBB1_4
96+
; CHECK-T1-NEXT: bmi .LBB1_4
9797
; CHECK-T1-NEXT: @ %bb.3:
9898
; CHECK-T1-NEXT: mov r6, r4
9999
; CHECK-T1-NEXT: .LBB1_4:
@@ -103,9 +103,8 @@ define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
103103
; CHECK-T1-NEXT: ldr r7, [sp, #24]
104104
; CHECK-T1-NEXT: adds r0, r0, r7
105105
; CHECK-T1-NEXT: adcs r1, r5
106-
; CHECK-T1-NEXT: cmp r1, #0
107106
; CHECK-T1-NEXT: mov r5, r2
108-
; CHECK-T1-NEXT: bge .LBB1_6
107+
; CHECK-T1-NEXT: bmi .LBB1_6
109108
; CHECK-T1-NEXT: @ %bb.5:
110109
; CHECK-T1-NEXT: mov r5, r4
111110
; CHECK-T1-NEXT: .LBB1_6:
@@ -144,23 +143,22 @@ define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
144143
; CHECK-T2-NEXT: .save {r7, lr}
145144
; CHECK-T2-NEXT: push {r7, lr}
146145
; CHECK-T2-NEXT: ldrd r2, r12, [sp, #8]
147-
; CHECK-T2-NEXT: cmp.w r1, #-1
146+
; CHECK-T2-NEXT: cmp r1, #0
148147
; CHECK-T2-NEXT: mov.w r3, #0
149148
; CHECK-T2-NEXT: mov.w lr, #0
150-
; CHECK-T2-NEXT: it gt
151-
; CHECK-T2-NEXT: movgt r3, #1
149+
; CHECK-T2-NEXT: it mi
150+
; CHECK-T2-NEXT: movmi r3, #1
152151
; CHECK-T2-NEXT: adds r0, r0, r2
153-
; CHECK-T2-NEXT: adc.w r2, r1, r12
154-
; CHECK-T2-NEXT: movs r1, #0
155-
; CHECK-T2-NEXT: cmp.w r2, #-1
156-
; CHECK-T2-NEXT: it gt
157-
; CHECK-T2-NEXT: movgt r1, #1
152+
; CHECK-T2-NEXT: adcs.w r2, r1, r12
153+
; CHECK-T2-NEXT: mov.w r1, #0
154+
; CHECK-T2-NEXT: it mi
155+
; CHECK-T2-NEXT: movmi r1, #1
158156
; CHECK-T2-NEXT: subs r1, r3, r1
159157
; CHECK-T2-NEXT: it ne
160158
; CHECK-T2-NEXT: movne r1, #1
161-
; CHECK-T2-NEXT: cmp.w r12, #-1
162-
; CHECK-T2-NEXT: it gt
163-
; CHECK-T2-NEXT: movgt.w lr, #1
159+
; CHECK-T2-NEXT: cmp.w r12, #0
160+
; CHECK-T2-NEXT: it mi
161+
; CHECK-T2-NEXT: movmi.w lr, #1
164162
; CHECK-T2-NEXT: sub.w r3, r3, lr
165163
; CHECK-T2-NEXT: clz r3, r3
166164
; CHECK-T2-NEXT: lsrs r3, r3, #5
@@ -186,15 +184,15 @@ define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
186184
; CHECK-ARM-NEXT: adds r0, r0, r2
187185
; CHECK-ARM-NEXT: mov r2, #0
188186
; CHECK-ARM-NEXT: adc lr, r1, r12
189-
; CHECK-ARM-NEXT: cmn r1, #1
187+
; CHECK-ARM-NEXT: cmp r1, #0
190188
; CHECK-ARM-NEXT: mov r1, #0
191-
; CHECK-ARM-NEXT: movwgt r1, #1
192-
; CHECK-ARM-NEXT: cmn lr, #1
193-
; CHECK-ARM-NEXT: movwgt r2, #1
189+
; CHECK-ARM-NEXT: movwmi r1, #1
190+
; CHECK-ARM-NEXT: cmp lr, #0
191+
; CHECK-ARM-NEXT: movwmi r2, #1
194192
; CHECK-ARM-NEXT: subs r2, r1, r2
195193
; CHECK-ARM-NEXT: movwne r2, #1
196-
; CHECK-ARM-NEXT: cmn r12, #1
197-
; CHECK-ARM-NEXT: movwgt r3, #1
194+
; CHECK-ARM-NEXT: cmp r12, #0
195+
; CHECK-ARM-NEXT: movwmi r3, #1
198196
; CHECK-ARM-NEXT: sub r1, r1, r3
199197
; CHECK-ARM-NEXT: clz r1, r1
200198
; CHECK-ARM-NEXT: lsr r1, r1, #5

‎llvm/test/CodeGen/ARM/ssub_sat.ll

Lines changed: 18 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -106,13 +106,13 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
106106
; CHECK-T1-NEXT: movs r0, #0
107107
; CHECK-T1-NEXT: cmp r3, #0
108108
; CHECK-T1-NEXT: mov r5, r4
109-
; CHECK-T1-NEXT: bge .LBB1_2
109+
; CHECK-T1-NEXT: bmi .LBB1_2
110110
; CHECK-T1-NEXT: @ %bb.1:
111111
; CHECK-T1-NEXT: mov r5, r0
112112
; CHECK-T1-NEXT: .LBB1_2:
113113
; CHECK-T1-NEXT: cmp r1, #0
114114
; CHECK-T1-NEXT: mov r7, r4
115-
; CHECK-T1-NEXT: bge .LBB1_4
115+
; CHECK-T1-NEXT: bmi .LBB1_4
116116
; CHECK-T1-NEXT: @ %bb.3:
117117
; CHECK-T1-NEXT: mov r7, r0
118118
; CHECK-T1-NEXT: .LBB1_4:
@@ -122,9 +122,8 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
122122
; CHECK-T1-NEXT: ldr r6, [sp] @ 4-byte Reload
123123
; CHECK-T1-NEXT: subs r6, r2, r6
124124
; CHECK-T1-NEXT: sbcs r1, r3
125-
; CHECK-T1-NEXT: cmp r1, #0
126125
; CHECK-T1-NEXT: mov r2, r4
127-
; CHECK-T1-NEXT: bge .LBB1_6
126+
; CHECK-T1-NEXT: bmi .LBB1_6
128127
; CHECK-T1-NEXT: @ %bb.5:
129128
; CHECK-T1-NEXT: mov r2, r0
130129
; CHECK-T1-NEXT: .LBB1_6:
@@ -163,23 +162,22 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
163162
; CHECK-T2: @ %bb.0:
164163
; CHECK-T2-NEXT: .save {r4, lr}
165164
; CHECK-T2-NEXT: push {r4, lr}
166-
; CHECK-T2-NEXT: cmp.w r3, #-1
165+
; CHECK-T2-NEXT: cmp r3, #0
167166
; CHECK-T2-NEXT: mov.w lr, #0
168-
; CHECK-T2-NEXT: it gt
169-
; CHECK-T2-NEXT: movgt.w lr, #1
170-
; CHECK-T2-NEXT: cmp.w r1, #-1
167+
; CHECK-T2-NEXT: it mi
168+
; CHECK-T2-NEXT: movmi.w lr, #1
169+
; CHECK-T2-NEXT: cmp r1, #0
171170
; CHECK-T2-NEXT: mov.w r4, #0
172171
; CHECK-T2-NEXT: mov.w r12, #0
173-
; CHECK-T2-NEXT: it gt
174-
; CHECK-T2-NEXT: movgt r4, #1
172+
; CHECK-T2-NEXT: it mi
173+
; CHECK-T2-NEXT: movmi r4, #1
175174
; CHECK-T2-NEXT: subs.w lr, r4, lr
176175
; CHECK-T2-NEXT: it ne
177176
; CHECK-T2-NEXT: movne.w lr, #1
178177
; CHECK-T2-NEXT: subs r0, r0, r2
179-
; CHECK-T2-NEXT: sbc.w r2, r1, r3
180-
; CHECK-T2-NEXT: cmp.w r2, #-1
181-
; CHECK-T2-NEXT: it gt
182-
; CHECK-T2-NEXT: movgt.w r12, #1
178+
; CHECK-T2-NEXT: sbcs.w r2, r1, r3
179+
; CHECK-T2-NEXT: it mi
180+
; CHECK-T2-NEXT: movmi.w r12, #1
183181
; CHECK-T2-NEXT: subs.w r1, r4, r12
184182
; CHECK-T2-NEXT: it ne
185183
; CHECK-T2-NEXT: movne r1, #1
@@ -199,19 +197,18 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
199197
; CHECK-ARM: @ %bb.0:
200198
; CHECK-ARM-NEXT: .save {r4, lr}
201199
; CHECK-ARM-NEXT: push {r4, lr}
202-
; CHECK-ARM-NEXT: cmn r3, #1
200+
; CHECK-ARM-NEXT: cmp r3, #0
203201
; CHECK-ARM-NEXT: mov lr, #0
204-
; CHECK-ARM-NEXT: movgt lr, #1
205-
; CHECK-ARM-NEXT: cmn r1, #1
202+
; CHECK-ARM-NEXT: movmi lr, #1
203+
; CHECK-ARM-NEXT: cmp r1, #0
206204
; CHECK-ARM-NEXT: mov r4, #0
207205
; CHECK-ARM-NEXT: mov r12, #0
208-
; CHECK-ARM-NEXT: movgt r4, #1
206+
; CHECK-ARM-NEXT: movmi r4, #1
209207
; CHECK-ARM-NEXT: subs lr, r4, lr
210208
; CHECK-ARM-NEXT: movne lr, #1
211209
; CHECK-ARM-NEXT: subs r0, r0, r2
212-
; CHECK-ARM-NEXT: sbc r2, r1, r3
213-
; CHECK-ARM-NEXT: cmn r2, #1
214-
; CHECK-ARM-NEXT: movgt r12, #1
210+
; CHECK-ARM-NEXT: sbcs r2, r1, r3
211+
; CHECK-ARM-NEXT: movmi r12, #1
215212
; CHECK-ARM-NEXT: subs r1, r4, r12
216213
; CHECK-ARM-NEXT: movne r1, #1
217214
; CHECK-ARM-NEXT: ands r3, lr, r1

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