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Jessica Paquette
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[AArch64][GlobalISel] Legalize narrow scalar FP arithmetic
Widen narrow fp arithmetic ops (e.g. G_FADD). When we don't have full FP16 support, widen to s32. Otherwise widen to s16. https://godbolt.org/z/TbT9Pqa7e Differential Revision: https://reviews.llvm.org/D108660
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‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

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@@ -194,7 +194,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
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.widenScalarToNextPow2(0);
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getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FNEG})
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.legalFor({s32, s64, v2s64, v4s32, v2s32})
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.legalFor({MinFPScalar, s32, s64, v2s64, v4s32, v2s32})
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.clampScalar(0, MinFPScalar, s64)
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.clampNumElements(0, v2s32, v4s32)
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.clampNumElements(0, v2s64, v2s64);
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‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith-fp16.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64-unknown-unknown -verify-machineinstrs -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=NO-FP16
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# RUN: llc -mtriple aarch64-unknown-unknown -verify-machineinstrs -mattr=+fullfp16 -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=FP16
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...
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---
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name: fadd
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $h0, $h1
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; NO-FP16-LABEL: name: fadd
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; NO-FP16: liveins: $h0, $h1
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; NO-FP16: %x:_(s16) = COPY $h0
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; NO-FP16: %y:_(s16) = COPY $h1
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; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %x(s16)
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; NO-FP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT %y(s16)
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; NO-FP16: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FPEXT]], [[FPEXT1]]
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; NO-FP16: %op:_(s16) = G_FPTRUNC [[FADD]](s32)
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; NO-FP16: $h0 = COPY %op(s16)
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; NO-FP16: RET_ReallyLR implicit $h0
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; FP16-LABEL: name: fadd
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; FP16: liveins: $h0, $h1
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; FP16: %x:_(s16) = COPY $h0
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; FP16: %y:_(s16) = COPY $h1
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; FP16: %op:_(s16) = G_FADD %x, %y
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; FP16: $h0 = COPY %op(s16)
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; FP16: RET_ReallyLR implicit $h0
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%x:_(s16) = COPY $h0
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%y:_(s16) = COPY $h1
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%op:_(s16) = G_FADD %x, %y
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$h0 = COPY %op(s16)
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RET_ReallyLR implicit $h0
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...
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---
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name: fsub
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $h0, $h1
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; NO-FP16-LABEL: name: fsub
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; NO-FP16: liveins: $h0, $h1
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; NO-FP16: %x:_(s16) = COPY $h0
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; NO-FP16: %y:_(s16) = COPY $h1
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; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %x(s16)
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; NO-FP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT %y(s16)
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; NO-FP16: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[FPEXT]], [[FPEXT1]]
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; NO-FP16: %op:_(s16) = G_FPTRUNC [[FSUB]](s32)
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; NO-FP16: $h0 = COPY %op(s16)
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; NO-FP16: RET_ReallyLR implicit $h0
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; FP16-LABEL: name: fsub
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; FP16: liveins: $h0, $h1
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; FP16: %x:_(s16) = COPY $h0
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; FP16: %y:_(s16) = COPY $h1
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; FP16: %op:_(s16) = G_FSUB %x, %y
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; FP16: $h0 = COPY %op(s16)
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; FP16: RET_ReallyLR implicit $h0
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%x:_(s16) = COPY $h0
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%y:_(s16) = COPY $h1
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%op:_(s16) = G_FSUB %x, %y
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$h0 = COPY %op(s16)
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RET_ReallyLR implicit $h0
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...
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---
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name: fmul
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $h0, $h1
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; NO-FP16-LABEL: name: fmul
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; NO-FP16: liveins: $h0, $h1
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; NO-FP16: %x:_(s16) = COPY $h0
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; NO-FP16: %y:_(s16) = COPY $h1
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; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %x(s16)
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; NO-FP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT %y(s16)
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; NO-FP16: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[FPEXT1]]
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; NO-FP16: %op:_(s16) = G_FPTRUNC [[FMUL]](s32)
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; NO-FP16: $h0 = COPY %op(s16)
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; NO-FP16: RET_ReallyLR implicit $h0
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; FP16-LABEL: name: fmul
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; FP16: liveins: $h0, $h1
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; FP16: %x:_(s16) = COPY $h0
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; FP16: %y:_(s16) = COPY $h1
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; FP16: %op:_(s16) = G_FMUL %x, %y
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; FP16: $h0 = COPY %op(s16)
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; FP16: RET_ReallyLR implicit $h0
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%x:_(s16) = COPY $h0
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%y:_(s16) = COPY $h1
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%op:_(s16) = G_FMUL %x, %y
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$h0 = COPY %op(s16)
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RET_ReallyLR implicit $h0
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...
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---
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name: fdiv
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $h0, $h1
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; NO-FP16-LABEL: name: fdiv
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; NO-FP16: liveins: $h0, $h1
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; NO-FP16: %x:_(s16) = COPY $h0
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; NO-FP16: %y:_(s16) = COPY $h1
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; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %x(s16)
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; NO-FP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT %y(s16)
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; NO-FP16: [[FDIV:%[0-9]+]]:_(s32) = G_FDIV [[FPEXT]], [[FPEXT1]]
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; NO-FP16: %op:_(s16) = G_FPTRUNC [[FDIV]](s32)
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; NO-FP16: $h0 = COPY %op(s16)
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; NO-FP16: RET_ReallyLR implicit $h0
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; FP16-LABEL: name: fdiv
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; FP16: liveins: $h0, $h1
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; FP16: %x:_(s16) = COPY $h0
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; FP16: %y:_(s16) = COPY $h1
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; FP16: %op:_(s16) = G_FDIV %x, %y
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; FP16: $h0 = COPY %op(s16)
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; FP16: RET_ReallyLR implicit $h0
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%x:_(s16) = COPY $h0
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%y:_(s16) = COPY $h1
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%op:_(s16) = G_FDIV %x, %y
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$h0 = COPY %op(s16)
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RET_ReallyLR implicit $h0
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...
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---
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name: fneg
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $h0
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; NO-FP16-LABEL: name: fneg
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; NO-FP16: liveins: $h0
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; NO-FP16: %x:_(s16) = COPY $h0
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; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %x(s16)
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; NO-FP16: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FPEXT]]
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; NO-FP16: %op:_(s16) = G_FPTRUNC [[FNEG]](s32)
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; NO-FP16: $h0 = COPY %op(s16)
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; NO-FP16: RET_ReallyLR implicit $h0
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; FP16-LABEL: name: fneg
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; FP16: liveins: $h0
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; FP16: %x:_(s16) = COPY $h0
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; FP16: %op:_(s16) = G_FNEG %x
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; FP16: $h0 = COPY %op(s16)
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; FP16: RET_ReallyLR implicit $h0
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%x:_(s16) = COPY $h0
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%op:_(s16) = G_FNEG %x
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$h0 = COPY %op(s16)
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RET_ReallyLR implicit $h0
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...

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