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Liqin Wengbenshi001
Liqin Weng
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benshi001
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[RISCV] Add CMOV isel pattern for (select (setgt X, Imm), Y, Z)
Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D122644
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-43
lines changed

4 files changed

+53
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‎llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -972,10 +972,11 @@ def : Pat<(select (XLenVT (setge GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1),
972972
def : Pat<(select (XLenVT (setle GPR:$y, GPR:$x)), GPR:$rs3, GPR:$rs1),
973973
(CMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
974974

975-
// setge X, 0 is canonicalized to setgt X, -1.
976-
// FIXME: This can be generalized to more immediates by using SLTI.
977-
def : Pat<(select (XLenVT (setgt GPR:$x, -1)), GPR:$rs3, GPR:$rs1),
978-
(CMOV GPR:$rs1, (SLT GPR:$x, X0), GPR:$rs3)>;
975+
// setge X, Imm is canonicalized to setgt X, (Imm - 1).
976+
def : Pat<(select (XLenVT (setgt GPR:$x, simm12_minus1_nonzero:$imm)), GPR:$rs3, GPR:$rs1),
977+
(CMOV GPR:$rs1, (SLTI GPR:$x, (ImmPlus1 simm12_minus1_nonzero:$imm)), GPR:$rs3)>;
978+
def : Pat<(select (XLenVT (setugt GPR:$x, simm12_minus1_nonzero:$imm)), GPR:$rs3, GPR:$rs1),
979+
(CMOV GPR:$rs1, (SLTIU GPR:$x, (ImmPlus1 simm12_minus1_nonzero:$imm)), GPR:$rs3)>;
979980

980981
def : Pat<(select GPR:$rs2, GPR:$rs1, GPR:$rs3),
981982
(CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;

‎llvm/test/CodeGen/RISCV/rv32zbt.ll

Lines changed: 8 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -336,8 +336,7 @@ define i32 @cmov_sgt_i32_constant_2046(i32 %a, i32 %b, i32 %c) nounwind {
336336
; RV32ZBT-LABEL: cmov_sgt_i32_constant_2046:
337337
; RV32ZBT: # %bb.0:
338338
; RV32ZBT-NEXT: slti a1, a1, 2047
339-
; RV32ZBT-NEXT: xori a1, a1, 1
340-
; RV32ZBT-NEXT: cmov a0, a1, a0, a2
339+
; RV32ZBT-NEXT: cmov a0, a1, a2, a0
341340
; RV32ZBT-NEXT: ret
342341
%tobool = icmp sgt i32 %b, 2046
343342
%cond = select i1 %tobool, i32 %a, i32 %c
@@ -358,8 +357,7 @@ define i32 @cmov_sgt_i32_constant_neg_2049(i32 %a, i32 %b, i32 %c) nounwind {
358357
; RV32ZBT-LABEL: cmov_sgt_i32_constant_neg_2049:
359358
; RV32ZBT: # %bb.0:
360359
; RV32ZBT-NEXT: slti a1, a1, -2048
361-
; RV32ZBT-NEXT: xori a1, a1, 1
362-
; RV32ZBT-NEXT: cmov a0, a1, a0, a2
360+
; RV32ZBT-NEXT: cmov a0, a1, a2, a0
363361
; RV32ZBT-NEXT: ret
364362
%tobool = icmp sgt i32 %b, -2049
365363
%cond = select i1 %tobool, i32 %a, i32 %c
@@ -398,8 +396,7 @@ define i32 @cmov_sge_i32_constant_2047(i32 %a, i32 %b, i32 %c) nounwind {
398396
; RV32ZBT-LABEL: cmov_sge_i32_constant_2047:
399397
; RV32ZBT: # %bb.0:
400398
; RV32ZBT-NEXT: slti a1, a1, 2047
401-
; RV32ZBT-NEXT: xori a1, a1, 1
402-
; RV32ZBT-NEXT: cmov a0, a1, a0, a2
399+
; RV32ZBT-NEXT: cmov a0, a1, a2, a0
403400
; RV32ZBT-NEXT: ret
404401
%tobool = icmp sge i32 %b, 2047
405402
%cond = select i1 %tobool, i32 %a, i32 %c
@@ -420,8 +417,7 @@ define i32 @cmov_sge_i32_constant_neg_2048(i32 %a, i32 %b, i32 %c) nounwind {
420417
; RV32ZBT-LABEL: cmov_sge_i32_constant_neg_2048:
421418
; RV32ZBT: # %bb.0:
422419
; RV32ZBT-NEXT: slti a1, a1, -2048
423-
; RV32ZBT-NEXT: xori a1, a1, 1
424-
; RV32ZBT-NEXT: cmov a0, a1, a0, a2
420+
; RV32ZBT-NEXT: cmov a0, a1, a2, a0
425421
; RV32ZBT-NEXT: ret
426422
%tobool = icmp sge i32 %b, -2048
427423
%cond = select i1 %tobool, i32 %a, i32 %c
@@ -519,8 +515,7 @@ define i32 @cmov_ugt_i32_constant_2046(i32 %a, i32 %b, i32 %c) nounwind {
519515
; RV32ZBT-LABEL: cmov_ugt_i32_constant_2046:
520516
; RV32ZBT: # %bb.0:
521517
; RV32ZBT-NEXT: sltiu a1, a1, 2047
522-
; RV32ZBT-NEXT: xori a1, a1, 1
523-
; RV32ZBT-NEXT: cmov a0, a1, a0, a2
518+
; RV32ZBT-NEXT: cmov a0, a1, a2, a0
524519
; RV32ZBT-NEXT: ret
525520
%tobool = icmp ugt i32 %b, 2046
526521
%cond = select i1 %tobool, i32 %a, i32 %c
@@ -541,8 +536,7 @@ define i32 @cmov_ugt_i32_constant_neg_2049(i32 %a, i32 %b, i32 %c) nounwind {
541536
; RV32ZBT-LABEL: cmov_ugt_i32_constant_neg_2049:
542537
; RV32ZBT: # %bb.0:
543538
; RV32ZBT-NEXT: sltiu a1, a1, -2048
544-
; RV32ZBT-NEXT: xori a1, a1, 1
545-
; RV32ZBT-NEXT: cmov a0, a1, a0, a2
539+
; RV32ZBT-NEXT: cmov a0, a1, a2, a0
546540
; RV32ZBT-NEXT: ret
547541
%tobool = icmp ugt i32 %b, 4294965247
548542
%cond = select i1 %tobool, i32 %a, i32 %c
@@ -581,8 +575,7 @@ define i32 @cmov_uge_i32_constant_2047(i32 %a, i32 %b, i32 %c) nounwind {
581575
; RV32ZBT-LABEL: cmov_uge_i32_constant_2047:
582576
; RV32ZBT: # %bb.0:
583577
; RV32ZBT-NEXT: sltiu a1, a1, 2047
584-
; RV32ZBT-NEXT: xori a1, a1, 1
585-
; RV32ZBT-NEXT: cmov a0, a1, a0, a2
578+
; RV32ZBT-NEXT: cmov a0, a1, a2, a0
586579
; RV32ZBT-NEXT: ret
587580
%tobool = icmp uge i32 %b, 2047
588581
%cond = select i1 %tobool, i32 %a, i32 %c
@@ -603,8 +596,7 @@ define i32 @cmov_uge_i32_constant_neg_2048(i32 %a, i32 %b, i32 %c) nounwind {
603596
; RV32ZBT-LABEL: cmov_uge_i32_constant_neg_2048:
604597
; RV32ZBT: # %bb.0:
605598
; RV32ZBT-NEXT: sltiu a1, a1, -2048
606-
; RV32ZBT-NEXT: xori a1, a1, 1
607-
; RV32ZBT-NEXT: cmov a0, a1, a0, a2
599+
; RV32ZBT-NEXT: cmov a0, a1, a2, a0
608600
; RV32ZBT-NEXT: ret
609601
%tobool = icmp uge i32 %b, 4294965248
610602
%cond = select i1 %tobool, i32 %a, i32 %c

‎llvm/test/CodeGen/RISCV/rv64zbt.ll

Lines changed: 8 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -404,8 +404,7 @@ define i64 @cmov_sgt_i64_constant_2046(i64 %a, i64 %b, i64 %c) nounwind {
404404
; RV64ZBT-LABEL: cmov_sgt_i64_constant_2046:
405405
; RV64ZBT: # %bb.0:
406406
; RV64ZBT-NEXT: slti a1, a1, 2047
407-
; RV64ZBT-NEXT: xori a1, a1, 1
408-
; RV64ZBT-NEXT: cmov a0, a1, a0, a2
407+
; RV64ZBT-NEXT: cmov a0, a1, a2, a0
409408
; RV64ZBT-NEXT: ret
410409
%tobool = icmp sgt i64 %b, 2046
411410
%cond = select i1 %tobool, i64 %a, i64 %c
@@ -426,8 +425,7 @@ define i64 @cmov_sgt_i64_constant_neg_2049(i64 %a, i64 %b, i64 %c) nounwind {
426425
; RV64ZBT-LABEL: cmov_sgt_i64_constant_neg_2049:
427426
; RV64ZBT: # %bb.0:
428427
; RV64ZBT-NEXT: slti a1, a1, -2048
429-
; RV64ZBT-NEXT: xori a1, a1, 1
430-
; RV64ZBT-NEXT: cmov a0, a1, a0, a2
428+
; RV64ZBT-NEXT: cmov a0, a1, a2, a0
431429
; RV64ZBT-NEXT: ret
432430
%tobool = icmp sgt i64 %b, -2049
433431
%cond = select i1 %tobool, i64 %a, i64 %c
@@ -466,8 +464,7 @@ define i64 @cmov_sge_i64_constant_2047(i64 %a, i64 %b, i64 %c) nounwind {
466464
; RV64ZBT-LABEL: cmov_sge_i64_constant_2047:
467465
; RV64ZBT: # %bb.0:
468466
; RV64ZBT-NEXT: slti a1, a1, 2047
469-
; RV64ZBT-NEXT: xori a1, a1, 1
470-
; RV64ZBT-NEXT: cmov a0, a1, a0, a2
467+
; RV64ZBT-NEXT: cmov a0, a1, a2, a0
471468
; RV64ZBT-NEXT: ret
472469
%tobool = icmp sge i64 %b, 2047
473470
%cond = select i1 %tobool, i64 %a, i64 %c
@@ -488,8 +485,7 @@ define i64 @cmov_sge_i64_constant_neg_2048(i64 %a, i64 %b, i64 %c) nounwind {
488485
; RV64ZBT-LABEL: cmov_sge_i64_constant_neg_2048:
489486
; RV64ZBT: # %bb.0:
490487
; RV64ZBT-NEXT: slti a1, a1, -2048
491-
; RV64ZBT-NEXT: xori a1, a1, 1
492-
; RV64ZBT-NEXT: cmov a0, a1, a0, a2
488+
; RV64ZBT-NEXT: cmov a0, a1, a2, a0
493489
; RV64ZBT-NEXT: ret
494490
%tobool = icmp sge i64 %b, -2048
495491
%cond = select i1 %tobool, i64 %a, i64 %c
@@ -587,8 +583,7 @@ define i64 @cmov_ugt_i64_constant_2046(i64 %a, i64 %b, i64 %c) nounwind {
587583
; RV64ZBT-LABEL: cmov_ugt_i64_constant_2046:
588584
; RV64ZBT: # %bb.0:
589585
; RV64ZBT-NEXT: sltiu a1, a1, 2047
590-
; RV64ZBT-NEXT: xori a1, a1, 1
591-
; RV64ZBT-NEXT: cmov a0, a1, a0, a2
586+
; RV64ZBT-NEXT: cmov a0, a1, a2, a0
592587
; RV64ZBT-NEXT: ret
593588
%tobool = icmp ugt i64 %b, 2046
594589
%cond = select i1 %tobool, i64 %a, i64 %c
@@ -609,8 +604,7 @@ define i64 @cmov_ugt_i64_constant_neg_2049(i64 %a, i64 %b, i64 %c) nounwind {
609604
; RV64ZBT-LABEL: cmov_ugt_i64_constant_neg_2049:
610605
; RV64ZBT: # %bb.0:
611606
; RV64ZBT-NEXT: sltiu a1, a1, -2048
612-
; RV64ZBT-NEXT: xori a1, a1, 1
613-
; RV64ZBT-NEXT: cmov a0, a1, a0, a2
607+
; RV64ZBT-NEXT: cmov a0, a1, a2, a0
614608
; RV64ZBT-NEXT: ret
615609
%tobool = icmp ugt i64 %b, 18446744073709549567
616610
%cond = select i1 %tobool, i64 %a, i64 %c
@@ -649,8 +643,7 @@ define i64 @cmov_uge_i64_constant_2047(i64 %a, i64 %b, i64 %c) nounwind {
649643
; RV64ZBT-LABEL: cmov_uge_i64_constant_2047:
650644
; RV64ZBT: # %bb.0:
651645
; RV64ZBT-NEXT: sltiu a1, a1, 2047
652-
; RV64ZBT-NEXT: xori a1, a1, 1
653-
; RV64ZBT-NEXT: cmov a0, a1, a0, a2
646+
; RV64ZBT-NEXT: cmov a0, a1, a2, a0
654647
; RV64ZBT-NEXT: ret
655648
%tobool = icmp uge i64 %b, 2047
656649
%cond = select i1 %tobool, i64 %a, i64 %c
@@ -671,8 +664,7 @@ define i64 @cmov_uge_i64_constant_neg_2048(i64 %a, i64 %b, i64 %c) nounwind {
671664
; RV64ZBT-LABEL: cmov_uge_i64_constant_neg_2048:
672665
; RV64ZBT: # %bb.0:
673666
; RV64ZBT-NEXT: sltiu a1, a1, -2048
674-
; RV64ZBT-NEXT: xori a1, a1, 1
675-
; RV64ZBT-NEXT: cmov a0, a1, a0, a2
667+
; RV64ZBT-NEXT: cmov a0, a1, a2, a0
676668
; RV64ZBT-NEXT: ret
677669
%tobool = icmp uge i64 %b, 18446744073709549568
678670
%cond = select i1 %tobool, i64 %a, i64 %c

‎llvm/test/CodeGen/RISCV/select-cc.ll

Lines changed: 32 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -62,11 +62,23 @@ define signext i32 @foo(i32 signext %a, i32 *%b) nounwind {
6262
; RV32I-NEXT: # %bb.21:
6363
; RV32I-NEXT: mv a0, a2
6464
; RV32I-NEXT: .LBB0_22:
65-
; RV32I-NEXT: lw a1, 0(a1)
65+
; RV32I-NEXT: lw a3, 0(a1)
6666
; RV32I-NEXT: bgez a2, .LBB0_24
6767
; RV32I-NEXT: # %bb.23:
68-
; RV32I-NEXT: mv a0, a1
68+
; RV32I-NEXT: mv a0, a3
6969
; RV32I-NEXT: .LBB0_24:
70+
; RV32I-NEXT: lw a3, 0(a1)
71+
; RV32I-NEXT: li a4, 1024
72+
; RV32I-NEXT: blt a4, a3, .LBB0_26
73+
; RV32I-NEXT: # %bb.25:
74+
; RV32I-NEXT: mv a0, a3
75+
; RV32I-NEXT: .LBB0_26:
76+
; RV32I-NEXT: lw a1, 0(a1)
77+
; RV32I-NEXT: li a3, 2046
78+
; RV32I-NEXT: bltu a3, a2, .LBB0_28
79+
; RV32I-NEXT: # %bb.27:
80+
; RV32I-NEXT: mv a0, a1
81+
; RV32I-NEXT: .LBB0_28:
7082
; RV32I-NEXT: ret
7183
;
7284
; RV32IBT-LABEL: foo:
@@ -98,14 +110,20 @@ define signext i32 @foo(i32 signext %a, i32 *%b) nounwind {
98110
; RV32IBT-NEXT: cmov a0, a4, a3, a0
99111
; RV32IBT-NEXT: lw a3, 0(a1)
100112
; RV32IBT-NEXT: slt a4, a0, a2
113+
; RV32IBT-NEXT: lw a5, 0(a1)
101114
; RV32IBT-NEXT: cmov a0, a4, a0, a2
115+
; RV32IBT-NEXT: slt a2, a3, a0
116+
; RV32IBT-NEXT: cmov a0, a2, a3, a0
117+
; RV32IBT-NEXT: slti a2, a5, 1
118+
; RV32IBT-NEXT: lw a3, 0(a1)
119+
; RV32IBT-NEXT: cmov a0, a2, a0, a5
102120
; RV32IBT-NEXT: lw a2, 0(a1)
103-
; RV32IBT-NEXT: slt a4, a3, a0
121+
; RV32IBT-NEXT: slti a4, a5, 0
104122
; RV32IBT-NEXT: cmov a0, a4, a3, a0
105123
; RV32IBT-NEXT: lw a1, 0(a1)
106-
; RV32IBT-NEXT: slti a3, a2, 1
107-
; RV32IBT-NEXT: cmov a0, a3, a0, a2
108-
; RV32IBT-NEXT: sltz a2, a2
124+
; RV32IBT-NEXT: slti a3, a2, 1025
125+
; RV32IBT-NEXT: cmov a0, a3, a2, a0
126+
; RV32IBT-NEXT: sltiu a2, a5, 2047
109127
; RV32IBT-NEXT: cmov a0, a2, a1, a0
110128
; RV32IBT-NEXT: ret
111129
%val1 = load volatile i32, i32* %b
@@ -156,7 +174,14 @@ define signext i32 @foo(i32 signext %a, i32 *%b) nounwind {
156174
%tst12 = icmp sgt i32 %val21, -1
157175
%val24 = select i1 %tst12, i32 %val22, i32 %val23
158176

159-
ret i32 %val24
177+
%val25 = load volatile i32, i32* %b
178+
%tst13 = icmp sgt i32 %val25, 1024
179+
%val26 = select i1 %tst13, i32 %val24, i32 %val25
180+
181+
%val27 = load volatile i32, i32* %b
182+
%tst14 = icmp ugt i32 %val21, 2046
183+
%val28 = select i1 %tst14, i32 %val26, i32 %val27
184+
ret i32 %val28
160185
}
161186

162187
; Test that we can ComputeNumSignBits across basic blocks when the live out is

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