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[Power9] Add __float128 support for compare operations
Added handling for the select f128. Differential Revision: https://reviews.llvm.org/D48294 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336548 91177308-0d34-0410-b5e6-96231b3b80d8
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4 files changed

+300
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‎lib/Target/PowerPC/PPCISelDAGToDAG.cpp

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3617,9 +3617,12 @@ SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
36173617
}
36183618
} else if (LHS.getValueType() == MVT::f32) {
36193619
Opc = PPC::FCMPUS;
3620-
} else {
3621-
assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
3620+
} else if (LHS.getValueType() == MVT::f64) {
36223621
Opc = PPCSubTarget->hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD;
3622+
} else {
3623+
assert(LHS.getValueType() == MVT::f128 && "Unknown vt!");
3624+
assert(PPCSubTarget->hasVSX() && "__float128 requires VSX");
3625+
Opc = PPC::XSCMPUQP;
36233626
}
36243627
return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0);
36253628
}
@@ -4564,6 +4567,8 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
45644567
SelectCCOp = PPC::SELECT_CC_VSFRC;
45654568
else
45664569
SelectCCOp = PPC::SELECT_CC_F8;
4570+
else if (N->getValueType(0) == MVT::f128)
4571+
SelectCCOp = PPC::SELECT_CC_F16;
45674572
else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f64)
45684573
SelectCCOp = PPC::SELECT_CC_QFRC;
45694574
else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f32)

‎lib/Target/PowerPC/PPCISelLowering.cpp

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -810,6 +810,13 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
810810
for (MVT FPT : MVT::fp_valuetypes())
811811
setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand);
812812
setOperationAction(ISD::FMA, MVT::f128, Legal);
813+
setCondCodeAction(ISD::SETULT, MVT::f128, Expand);
814+
setCondCodeAction(ISD::SETUGT, MVT::f128, Expand);
815+
setCondCodeAction(ISD::SETUEQ, MVT::f128, Expand);
816+
setCondCodeAction(ISD::SETOGE, MVT::f128, Expand);
817+
setCondCodeAction(ISD::SETOLE, MVT::f128, Expand);
818+
setCondCodeAction(ISD::SETONE, MVT::f128, Expand);
819+
setOperationAction(ISD::SELECT, MVT::f128, Expand);
813820
setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
814821
setOperationAction(ISD::FP_ROUND, MVT::f32, Legal);
815822
setTruncStoreAction(MVT::f128, MVT::f64, Expand);
@@ -10206,6 +10213,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1020610213
MI.getOpcode() == PPC::SELECT_CC_I8 ||
1020710214
MI.getOpcode() == PPC::SELECT_CC_F4 ||
1020810215
MI.getOpcode() == PPC::SELECT_CC_F8 ||
10216+
MI.getOpcode() == PPC::SELECT_CC_F16 ||
1020910217
MI.getOpcode() == PPC::SELECT_CC_QFRC ||
1021010218
MI.getOpcode() == PPC::SELECT_CC_QSRC ||
1021110219
MI.getOpcode() == PPC::SELECT_CC_QBRC ||
@@ -10217,6 +10225,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1021710225
MI.getOpcode() == PPC::SELECT_I8 ||
1021810226
MI.getOpcode() == PPC::SELECT_F4 ||
1021910227
MI.getOpcode() == PPC::SELECT_F8 ||
10228+
MI.getOpcode() == PPC::SELECT_F16 ||
1022010229
MI.getOpcode() == PPC::SELECT_QFRC ||
1022110230
MI.getOpcode() == PPC::SELECT_QSRC ||
1022210231
MI.getOpcode() == PPC::SELECT_QBRC ||
@@ -10252,6 +10261,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1025210261

1025310262
if (MI.getOpcode() == PPC::SELECT_I4 || MI.getOpcode() == PPC::SELECT_I8 ||
1025410263
MI.getOpcode() == PPC::SELECT_F4 || MI.getOpcode() == PPC::SELECT_F8 ||
10264+
MI.getOpcode() == PPC::SELECT_F16 ||
1025510265
MI.getOpcode() == PPC::SELECT_QFRC ||
1025610266
MI.getOpcode() == PPC::SELECT_QSRC ||
1025710267
MI.getOpcode() == PPC::SELECT_QBRC ||

‎lib/Target/PowerPC/PPCInstrInfo.td

Lines changed: 58 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1216,6 +1216,9 @@ let usesCustomInserter = 1, // Expanded after instruction selection.
12161216
def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
12171217
i32imm:$BROPC), "#SELECT_CC_F8",
12181218
[]>;
1219+
def SELECT_CC_F16 : Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
1220+
i32imm:$BROPC), "#SELECT_CC_F16",
1221+
[]>;
12191222
def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
12201223
i32imm:$BROPC), "#SELECT_CC_VRRC",
12211224
[]>;
@@ -1234,6 +1237,9 @@ let usesCustomInserter = 1, // Expanded after instruction selection.
12341237
def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
12351238
f8rc:$T, f8rc:$F), "#SELECT_F8",
12361239
[(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
1240+
def SELECT_F16 : Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
1241+
vrrc:$T, vrrc:$F), "#SELECT_F16",
1242+
[(set f128:$dst, (select i1:$cond, f128:$T, f128:$F))]>;
12371243
def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
12381244
vrrc:$T, vrrc:$F), "#SELECT_VRRC",
12391245
[(set v4i32:$dst,
@@ -3622,6 +3628,37 @@ defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
36223628
defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
36233629
(EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
36243630

3631+
// SETCC for f128.
3632+
def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETOLT)),
3633+
(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_lt)>;
3634+
def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETLT)),
3635+
(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_lt)>;
3636+
def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETOGT)),
3637+
(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_gt)>;
3638+
def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETGT)),
3639+
(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_gt)>;
3640+
def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETOEQ)),
3641+
(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_eq)>;
3642+
def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETEQ)),
3643+
(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_eq)>;
3644+
def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETUO)),
3645+
(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_un)>;
3646+
3647+
defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETUGE)),
3648+
(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_lt)>;
3649+
defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETGE)),
3650+
(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_lt)>;
3651+
defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETULE)),
3652+
(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_gt)>;
3653+
defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETLE)),
3654+
(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_gt)>;
3655+
defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETUNE)),
3656+
(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_eq)>;
3657+
defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETNE)),
3658+
(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_eq)>;
3659+
defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETO)),
3660+
(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_un)>;
3661+
36253662
// match select on i1 variables:
36263663
def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
36273664
(CROR (CRAND $cond , $tval),
@@ -3746,6 +3783,27 @@ def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)),
37463783
def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
37473784
(SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
37483785

3786+
def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLT)),
3787+
(SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>;
3788+
def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULT)),
3789+
(SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>;
3790+
def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLE)),
3791+
(SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>;
3792+
def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULE)),
3793+
(SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>;
3794+
def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETEQ)),
3795+
(SELECT_F16 (CREQV $lhs, $rhs), $tval, $fval)>;
3796+
def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGE)),
3797+
(SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>;
3798+
def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGE)),
3799+
(SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>;
3800+
def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGT)),
3801+
(SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>;
3802+
def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGT)),
3803+
(SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>;
3804+
def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETNE)),
3805+
(SELECT_F16 (CRXOR $lhs, $rhs), $tval, $fval)>;
3806+
37493807
def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
37503808
(SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
37513809
def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULT)),

‎test/CodeGen/PowerPC/f128-compare.ll

Lines changed: 225 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,225 @@
1+
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
2+
; RUN: -enable-ppc-quad-precision -verify-machineinstrs < %s | FileCheck %s
3+
4+
@a_qp = common global fp128 0xL00000000000000000000000000000000, align 16
5+
@b_qp = common global fp128 0xL00000000000000000000000000000000, align 16
6+
7+
; Function Attrs: noinline nounwind optnone
8+
define signext i32 @greater_qp() {
9+
entry:
10+
%0 = load fp128, fp128* @a_qp, align 16
11+
%1 = load fp128, fp128* @b_qp, align 16
12+
%cmp = fcmp ogt fp128 %0, %1
13+
%conv = zext i1 %cmp to i32
14+
ret i32 %conv
15+
; CHECK-LABEL: greater_qp
16+
; CHECK: xscmpuqp
17+
; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, 1
18+
; CHECK: blr
19+
}
20+
21+
; Function Attrs: noinline nounwind optnone
22+
define signext i32 @less_qp() {
23+
entry:
24+
%0 = load fp128, fp128* @a_qp, align 16
25+
%1 = load fp128, fp128* @b_qp, align 16
26+
%cmp = fcmp olt fp128 %0, %1
27+
%conv = zext i1 %cmp to i32
28+
ret i32 %conv
29+
; CHECK-LABEL: less_qp
30+
; CHECK: xscmpuqp
31+
; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, 0
32+
; CHECK: blr
33+
}
34+
35+
; Function Attrs: noinline nounwind optnone
36+
define signext i32 @greater_eq_qp() {
37+
entry:
38+
%0 = load fp128, fp128* @a_qp, align 16
39+
%1 = load fp128, fp128* @b_qp, align 16
40+
%cmp = fcmp oge fp128 %0, %1
41+
%conv = zext i1 %cmp to i32
42+
ret i32 %conv
43+
; CHECK-LABEL: greater_eq_qp
44+
; CHECK: xscmpuqp
45+
; CHECK: cror [[REG:[0-9]+]], {{[0-9]+}}, 0
46+
; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, [[REG]]
47+
; CHECK: blr
48+
}
49+
50+
; Function Attrs: noinline nounwind optnone
51+
define signext i32 @less_eq_qp() {
52+
entry:
53+
%0 = load fp128, fp128* @a_qp, align 16
54+
%1 = load fp128, fp128* @b_qp, align 16
55+
%cmp = fcmp ole fp128 %0, %1
56+
%conv = zext i1 %cmp to i32
57+
ret i32 %conv
58+
; CHECK-LABEL: less_eq_qp
59+
; CHECK: xscmpuqp
60+
; CHECK: cror [[REG:[0-9]+]], {{[0-9]+}}, 1
61+
; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, [[REG]]
62+
; CHECK: blr
63+
}
64+
65+
; Function Attrs: noinline nounwind optnone
66+
define signext i32 @equal_qp() {
67+
entry:
68+
%0 = load fp128, fp128* @a_qp, align 16
69+
%1 = load fp128, fp128* @b_qp, align 16
70+
%cmp = fcmp oeq fp128 %0, %1
71+
%conv = zext i1 %cmp to i32
72+
ret i32 %conv
73+
; CHECK-LABEL: equal_qp
74+
; CHECK: xscmpuqp
75+
; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, 2
76+
; CHECK: blr
77+
}
78+
79+
; Function Attrs: noinline nounwind optnone
80+
define signext i32 @not_greater_qp() {
81+
entry:
82+
%0 = load fp128, fp128* @a_qp, align 16
83+
%1 = load fp128, fp128* @b_qp, align 16
84+
%cmp = fcmp ogt fp128 %0, %1
85+
%lnot = xor i1 %cmp, true
86+
%lnot.ext = zext i1 %lnot to i32
87+
ret i32 %lnot.ext
88+
; CHECK-LABEL: not_greater_qp
89+
; CHECK: xscmpuqp
90+
; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, 1
91+
; CHECK: blr
92+
}
93+
94+
; Function Attrs: noinline nounwind optnone
95+
define signext i32 @not_less_qp() {
96+
entry:
97+
%0 = load fp128, fp128* @a_qp, align 16
98+
%1 = load fp128, fp128* @b_qp, align 16
99+
%cmp = fcmp olt fp128 %0, %1
100+
%lnot = xor i1 %cmp, true
101+
%lnot.ext = zext i1 %lnot to i32
102+
ret i32 %lnot.ext
103+
; CHECK-LABEL: not_less_qp
104+
; CHECK: xscmpuqp
105+
; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, 0
106+
; CHECK: blr
107+
}
108+
109+
; Function Attrs: noinline nounwind optnone
110+
define signext i32 @not_greater_eq_qp() {
111+
entry:
112+
%0 = load fp128, fp128* @a_qp, align 16
113+
%1 = load fp128, fp128* @b_qp, align 16
114+
%cmp = fcmp oge fp128 %0, %1
115+
%lnot = xor i1 %cmp, true
116+
%lnot.ext = zext i1 %lnot to i32
117+
ret i32 %lnot.ext
118+
; CHECK-LABEL: not_greater_eq_qp
119+
; CHECK: xscmpuqp
120+
; CHECK: crnor [[REG:[0-9]+]], 0, {{[0-9]+}}
121+
; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, [[REG]]
122+
; CHECK: blr
123+
}
124+
125+
; Function Attrs: noinline nounwind optnone
126+
define signext i32 @not_less_eq_qp() {
127+
entry:
128+
%0 = load fp128, fp128* @a_qp, align 16
129+
%1 = load fp128, fp128* @b_qp, align 16
130+
%cmp = fcmp ole fp128 %0, %1
131+
%lnot = xor i1 %cmp, true
132+
%lnot.ext = zext i1 %lnot to i32
133+
ret i32 %lnot.ext
134+
; CHECK-LABEL: not_less_eq_qp
135+
; CHECK: xscmpuqp
136+
; CHECK: crnor [[REG:[0-9]+]], 1, {{[0-9]+}}
137+
; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, [[REG]]
138+
; CHECK: blr
139+
}
140+
141+
; Function Attrs: noinline nounwind optnone
142+
define signext i32 @not_equal_qp() {
143+
entry:
144+
%0 = load fp128, fp128* @a_qp, align 16
145+
%1 = load fp128, fp128* @b_qp, align 16
146+
%cmp = fcmp une fp128 %0, %1
147+
%conv = zext i1 %cmp to i32
148+
ret i32 %conv
149+
; CHECK-LABEL: not_equal_qp
150+
; CHECK: xscmpuqp
151+
; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, 2
152+
; CHECK: blr
153+
}
154+
155+
; Function Attrs: norecurse nounwind readonly
156+
define fp128 @greater_sel_qp() {
157+
entry:
158+
%0 = load fp128, fp128* @a_qp, align 16
159+
%1 = load fp128, fp128* @b_qp, align 16
160+
%cmp = fcmp ogt fp128 %0, %1
161+
%cond = select i1 %cmp, fp128 %0, fp128 %1
162+
ret fp128 %cond
163+
; CHECK-LABEL: greater_sel_qp
164+
; CHECK: xscmpuqp [[REG:[0-9]+]]
165+
; CHECK: bgtlr [[REG]]
166+
; CHECK: blr
167+
}
168+
169+
; Function Attrs: noinline nounwind optnone
170+
define fp128 @less_sel_qp() {
171+
entry:
172+
%0 = load fp128, fp128* @a_qp, align 16
173+
%1 = load fp128, fp128* @b_qp, align 16
174+
%cmp = fcmp olt fp128 %0, %1
175+
%cond = select i1 %cmp, fp128 %0, fp128 %1
176+
ret fp128 %cond
177+
; CHECK-LABEL: less_sel_qp
178+
; CHECK: xscmpuqp [[REG:[0-9]+]]
179+
; CHECK: bltlr [[REG]]
180+
; CHECK: blr
181+
}
182+
183+
; Function Attrs: noinline nounwind optnone
184+
define fp128 @greater_eq_sel_qp() {
185+
entry:
186+
%0 = load fp128, fp128* @a_qp, align 16
187+
%1 = load fp128, fp128* @b_qp, align 16
188+
%cmp = fcmp oge fp128 %0, %1
189+
%cond = select i1 %cmp, fp128 %0, fp128 %1
190+
ret fp128 %cond
191+
; CHECK-LABEL: greater_eq_sel_qp
192+
; CHECK: xscmpuqp
193+
; CHECK: crnor [[REG:[0-9]+]], {{[0-9]+}}, 0
194+
; CHECK: bclr {{[0-9]+}}, [[REG]]
195+
; CHECK: blr
196+
}
197+
198+
; Function Attrs: noinline nounwind optnone
199+
define fp128 @less_eq_sel_qp() {
200+
entry:
201+
%0 = load fp128, fp128* @a_qp, align 16
202+
%1 = load fp128, fp128* @b_qp, align 16
203+
%cmp = fcmp ole fp128 %0, %1
204+
%cond = select i1 %cmp, fp128 %0, fp128 %1
205+
ret fp128 %cond
206+
; CHECK-LABEL: less_eq_sel_qp
207+
; CHECK: xscmpuqp
208+
; CHECK: crnor [[REG:[0-9]+]], {{[0-9]+}}, 1
209+
; CHECK: bclr {{[0-9]+}}, [[REG]]
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; CHECK: blr
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}
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; Function Attrs: noinline nounwind optnone
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define fp128 @equal_sel_qp() {
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entry:
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%0 = load fp128, fp128* @a_qp, align 16
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%1 = load fp128, fp128* @b_qp, align 16
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%cmp = fcmp oeq fp128 %0, %1
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%cond = select i1 %cmp, fp128 %0, fp128 %1
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ret fp128 %cond
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; CHECK-LABEL: equal_sel_qp
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; CHECK: xscmpuqp [[REG:[0-9]+]]
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; CHECK: beqlr [[REG]]
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; CHECK: blr
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}

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