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Commit 1526258

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Eli Friedman
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[ARM] Replace some C++ selection code with TableGen patterns. NFC.
Differential Revision: https://reviews.llvm.org/D30794 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297768 91177308-0d34-0410-b5e6-96231b3b80d8
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-64
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5 files changed

+33
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‎lib/Target/ARM/ARMISelDAGToDAG.cpp

Lines changed: 0 additions & 57 deletions
Original file line numberDiff line numberDiff line change
@@ -244,7 +244,6 @@ class ARMDAGToDAGISel : public SelectionDAGISel {
244244

245245
bool tryInlineAsm(SDNode *N);
246246

247-
void SelectConcatVector(SDNode *N);
248247
void SelectCMPZ(SDNode *N, bool &SwitchEQNEToPLMI);
249248

250249
void SelectCMP_SWAP(SDNode *N);
@@ -2585,15 +2584,6 @@ void ARMDAGToDAGISel::SelectCMP_SWAP(SDNode *N) {
25852584
CurDAG->RemoveDeadNode(N);
25862585
}
25872586

2588-
void ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
2589-
// The only time a CONCAT_VECTORS operation can have legal types is when
2590-
// two 64-bit vectors are concatenated to a 128-bit vector.
2591-
EVT VT = N->getValueType(0);
2592-
if (!VT.is128BitVector() || N->getNumOperands() != 2)
2593-
llvm_unreachable("unexpected CONCAT_VECTORS");
2594-
ReplaceNode(N, createDRegPairNode(VT, N->getOperand(0), N->getOperand(1)));
2595-
}
2596-
25972587
static Optional<std::pair<unsigned, unsigned>>
25982588
getContiguousRangeOfSetBits(const APInt &A) {
25992589
unsigned FirstOne = A.getBitWidth() - A.countLeadingZeros() - 1;
@@ -2900,49 +2890,6 @@ void ARMDAGToDAGISel::Select(SDNode *N) {
29002890

29012891
break;
29022892
}
2903-
case ARMISD::VMOVRRD:
2904-
ReplaceNode(N, CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
2905-
N->getOperand(0), getAL(CurDAG, dl),
2906-
CurDAG->getRegister(0, MVT::i32)));
2907-
return;
2908-
case ISD::UMUL_LOHI: {
2909-
if (Subtarget->isThumb1Only())
2910-
break;
2911-
if (Subtarget->isThumb()) {
2912-
SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2913-
getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32) };
2914-
ReplaceNode(
2915-
N, CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops));
2916-
return;
2917-
} else {
2918-
SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2919-
getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32),
2920-
CurDAG->getRegister(0, MVT::i32) };
2921-
ReplaceNode(N, CurDAG->getMachineNode(
2922-
Subtarget->hasV6Ops() ? ARM::UMULL : ARM::UMULLv5, dl,
2923-
MVT::i32, MVT::i32, Ops));
2924-
return;
2925-
}
2926-
}
2927-
case ISD::SMUL_LOHI: {
2928-
if (Subtarget->isThumb1Only())
2929-
break;
2930-
if (Subtarget->isThumb()) {
2931-
SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2932-
getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32) };
2933-
ReplaceNode(
2934-
N, CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops));
2935-
return;
2936-
} else {
2937-
SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2938-
getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32),
2939-
CurDAG->getRegister(0, MVT::i32) };
2940-
ReplaceNode(N, CurDAG->getMachineNode(
2941-
Subtarget->hasV6Ops() ? ARM::SMULL : ARM::SMULLv5, dl,
2942-
MVT::i32, MVT::i32, Ops));
2943-
return;
2944-
}
2945-
}
29462893
case ARMISD::UMAAL: {
29472894
unsigned Opc = Subtarget->isThumb() ? ARM::t2UMAAL : ARM::UMAAL;
29482895
SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
@@ -3836,10 +3783,6 @@ void ARMDAGToDAGISel::Select(SDNode *N) {
38363783
return;
38373784
}
38383785

3839-
case ISD::CONCAT_VECTORS:
3840-
SelectConcatVector(N);
3841-
return;
3842-
38433786
case ISD::ATOMIC_CMP_SWAP:
38443787
SelectCMP_SWAP(N);
38453788
return;

‎lib/Target/ARM/ARMInstrInfo.td

Lines changed: 12 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3956,27 +3956,35 @@ let hasSideEffects = 0 in {
39563956
let isCommutable = 1 in {
39573957
def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
39583958
(ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3959-
"smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3959+
"smull", "\t$RdLo, $RdHi, $Rn, $Rm",
3960+
[(set GPR:$RdLo, GPR:$RdHi,
3961+
(smullohi GPR:$Rn, GPR:$Rm))]>,
39603962
Requires<[IsARM, HasV6]>,
39613963
Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>;
39623964

39633965
def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
39643966
(ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3965-
"umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3967+
"umull", "\t$RdLo, $RdHi, $Rn, $Rm",
3968+
[(set GPR:$RdLo, GPR:$RdHi,
3969+
(umullohi GPR:$Rn, GPR:$Rm))]>,
39663970
Requires<[IsARM, HasV6]>,
39673971
Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL]>;
39683972

39693973
let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
39703974
def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
39713975
(ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3972-
4, IIC_iMUL64, [],
3976+
4, IIC_iMUL64,
3977+
[(set GPR:$RdLo, GPR:$RdHi,
3978+
(smullohi GPR:$Rn, GPR:$Rm))],
39733979
(SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
39743980
Requires<[IsARM, NoV6]>,
39753981
Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>;
39763982

39773983
def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
39783984
(ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3979-
4, IIC_iMUL64, [],
3985+
4, IIC_iMUL64,
3986+
[(set GPR:$RdLo, GPR:$RdHi,
3987+
(umullohi GPR:$Rn, GPR:$Rm))],
39803988
(UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
39813989
Requires<[IsARM, NoV6]>,
39823990
Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>;

‎lib/Target/ARM/ARMInstrNEON.td

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7139,6 +7139,17 @@ let Predicates = [IsBE] in {
71397139
(f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)), dsub_0))>;
71407140
}
71417141

7142+
def : Pat<(v2i64 (concat_vectors DPR:$Dn, DPR:$Dm)),
7143+
(REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)>;
7144+
def : Pat<(v4i32 (concat_vectors DPR:$Dn, DPR:$Dm)),
7145+
(REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)>;
7146+
def : Pat<(v8i16 (concat_vectors DPR:$Dn, DPR:$Dm)),
7147+
(REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)>;
7148+
def : Pat<(v16i8 (concat_vectors DPR:$Dn, DPR:$Dm)),
7149+
(REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)>;
7150+
def : Pat<(v4f32 (concat_vectors DPR:$Dn, DPR:$Dm)),
7151+
(REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)>;
7152+
71427153
//===----------------------------------------------------------------------===//
71437154
// Assembler aliases
71447155
//

‎lib/Target/ARM/ARMInstrThumb2.td

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2603,8 +2603,12 @@ def t2MLS: T2FourRegMLA<0b0001, "mls",
26032603
// Extra precision multiplies with low / high results
26042604
let hasSideEffects = 0 in {
26052605
let isCommutable = 1 in {
2606-
def t2SMULL : T2MulLong<0b000, 0b0000, "smull", []>;
2607-
def t2UMULL : T2MulLong<0b010, 0b0000, "umull", []>;
2606+
def t2SMULL : T2MulLong<0b000, 0b0000, "smull",
2607+
[(set rGPR:$RdLo, rGPR:$RdHi,
2608+
(smullohi rGPR:$Rn, rGPR:$Rm))]>;
2609+
def t2UMULL : T2MulLong<0b010, 0b0000, "umull",
2610+
[(set rGPR:$RdLo, rGPR:$RdHi,
2611+
(umullohi rGPR:$Rn, rGPR:$Rm))]>;
26082612
} // isCommutable
26092613

26102614
// Multiply + accumulate

‎lib/Target/ARM/ARMInstrVFP.td

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,11 +14,14 @@
1414
def SDT_CMPFP0 : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisVT<1, i32>]>;
1515
def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
1616
SDTCisSameAs<1, 2>]>;
17+
def SDT_VMOVRRD : SDTypeProfile<2, 1, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
18+
SDTCisVT<2, f64>]>;
1719

1820
def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>;
1921
def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMFCmp, [SDNPOutGlue]>;
2022
def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>;
2123
def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
24+
def arm_fmrrd : SDNode<"ARMISD::VMOVRRD", SDT_VMOVRRD>;
2225

2326
//===----------------------------------------------------------------------===//
2427
// Operand Definitions.
@@ -1054,7 +1057,7 @@ let hasSideEffects = 0 in {
10541057
def VMOVRRD : AVConv3I<0b11000101, 0b1011,
10551058
(outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
10561059
IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
1057-
[/* FIXME: Can't write pattern for multiple result instr*/]>,
1060+
[(set GPR:$Rt, GPR:$Rt2, (arm_fmrrd DPR:$Dm))]>,
10581061
Sched<[WriteFPMOV]> {
10591062
// Instruction operands.
10601063
bits<5> Dm;

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