@@ -132,32 +132,24 @@ class ExegesisX86Target : public ExegesisTarget {
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std::vector<llvm::MCInst>
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setRegToConstant (unsigned Reg) const override {
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- if (llvm::X86::GR8RegClass.contains (Reg)) {
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+ if (llvm::X86::GR8RegClass.contains (Reg))
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return {llvm::MCInstBuilder (llvm::X86::MOV8ri).addReg (Reg).addImm (1 )};
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- }
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- if (llvm::X86::GR16RegClass.contains (Reg)) {
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+ if (llvm::X86::GR16RegClass.contains (Reg))
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return {llvm::MCInstBuilder (llvm::X86::MOV16ri).addReg (Reg).addImm (1 )};
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- }
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- if (llvm::X86::GR32RegClass.contains (Reg)) {
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+ if (llvm::X86::GR32RegClass.contains (Reg))
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return {llvm::MCInstBuilder (llvm::X86::MOV32ri).addReg (Reg).addImm (1 )};
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- }
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- if (llvm::X86::GR64RegClass.contains (Reg)) {
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+ if (llvm::X86::GR64RegClass.contains (Reg))
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return {llvm::MCInstBuilder (llvm::X86::MOV64ri32).addReg (Reg).addImm (1 )};
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- }
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- if (llvm::X86::VR128XRegClass.contains (Reg)) {
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+ if (llvm::X86::VR128XRegClass.contains (Reg))
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return setVectorRegToConstant (Reg, 16 , llvm::X86::VMOVDQUrm);
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- }
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- if (llvm::X86::VR256XRegClass.contains (Reg)) {
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+ if (llvm::X86::VR256XRegClass.contains (Reg))
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return setVectorRegToConstant (Reg, 32 , llvm::X86::VMOVDQUYrm);
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- }
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- if (llvm::X86::VR512RegClass.contains (Reg)) {
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+ if (llvm::X86::VR512RegClass.contains (Reg))
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return setVectorRegToConstant (Reg, 64 , llvm::X86::VMOVDQU64Zrm);
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- }
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if (llvm::X86::RFP32RegClass.contains (Reg) ||
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llvm::X86::RFP64RegClass.contains (Reg) ||
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- llvm::X86::RFP80RegClass.contains (Reg)) {
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+ llvm::X86::RFP80RegClass.contains (Reg))
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return setVectorRegToConstant (Reg, 8 , llvm::X86::LD_Fp64m);
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- }
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return {};
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}
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