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Commit 497f7d2

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author
Sjoerd Meijer
committed
[ARM][NFC] Replaced tab-characters in test file vtrn.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339251 91177308-0d34-0410-b5e6-96231b3b80d8
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‎test/CodeGen/ARM/vtrn.ll

Lines changed: 100 additions & 100 deletions
Original file line numberDiff line numberDiff line change
@@ -9,12 +9,12 @@ define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
99
; CHECK-NEXT: vadd.i8 d16, d17, d16
1010
; CHECK-NEXT: vmov r0, r1, d16
1111
; CHECK-NEXT: mov pc, lr
12-
%tmp1 = load <8 x i8>, <8 x i8>* %A
13-
%tmp2 = load <8 x i8>, <8 x i8>* %B
14-
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
15-
%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
16-
%tmp5 = add <8 x i8> %tmp3, %tmp4
17-
ret <8 x i8> %tmp5
12+
%tmp1 = load <8 x i8>, <8 x i8>* %A
13+
%tmp2 = load <8 x i8>, <8 x i8>* %B
14+
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
15+
%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
16+
%tmp5 = add <8 x i8> %tmp3, %tmp4
17+
ret <8 x i8> %tmp5
1818
}
1919

2020
define <16 x i8> @vtrni8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
@@ -26,10 +26,10 @@ define <16 x i8> @vtrni8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
2626
; CHECK-NEXT: vmov r0, r1, [[LDR0]]
2727
; CHECK-NEXT: vmov r2, r3, [[LDR1]]
2828
; CHECK-NEXT: mov pc, lr
29-
%tmp1 = load <8 x i8>, <8 x i8>* %A
30-
%tmp2 = load <8 x i8>, <8 x i8>* %B
31-
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14, i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
32-
ret <16 x i8> %tmp3
29+
%tmp1 = load <8 x i8>, <8 x i8>* %A
30+
%tmp2 = load <8 x i8>, <8 x i8>* %B
31+
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14, i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
32+
ret <16 x i8> %tmp3
3333
}
3434

3535
define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
@@ -41,12 +41,12 @@ define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
4141
; CHECK-NEXT: vadd.i16 d16, d17, d16
4242
; CHECK-NEXT: vmov r0, r1, d16
4343
; CHECK-NEXT: mov pc, lr
44-
%tmp1 = load <4 x i16>, <4 x i16>* %A
45-
%tmp2 = load <4 x i16>, <4 x i16>* %B
46-
%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
47-
%tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
48-
%tmp5 = add <4 x i16> %tmp3, %tmp4
49-
ret <4 x i16> %tmp5
44+
%tmp1 = load <4 x i16>, <4 x i16>* %A
45+
%tmp2 = load <4 x i16>, <4 x i16>* %B
46+
%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
47+
%tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
48+
%tmp5 = add <4 x i16> %tmp3, %tmp4
49+
ret <4 x i16> %tmp5
5050
}
5151

5252
define <8 x i16> @vtrni16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind {
@@ -58,10 +58,10 @@ define <8 x i16> @vtrni16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind {
5858
; CHECK-NEXT: vmov r0, r1, [[LDR0]]
5959
; CHECK-NEXT: vmov r2, r3, [[LDR1]]
6060
; CHECK-NEXT: mov pc, lr
61-
%tmp1 = load <4 x i16>, <4 x i16>* %A
62-
%tmp2 = load <4 x i16>, <4 x i16>* %B
63-
%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 0, i32 4, i32 2, i32 6, i32 1, i32 5, i32 3, i32 7>
64-
ret <8 x i16> %tmp3
61+
%tmp1 = load <4 x i16>, <4 x i16>* %A
62+
%tmp2 = load <4 x i16>, <4 x i16>* %B
63+
%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 0, i32 4, i32 2, i32 6, i32 1, i32 5, i32 3, i32 7>
64+
ret <8 x i16> %tmp3
6565
}
6666

6767
define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
@@ -73,12 +73,12 @@ define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
7373
; CHECK-NEXT: vmul.i32 d16, d17, d16
7474
; CHECK-NEXT: vmov r0, r1, d16
7575
; CHECK-NEXT: mov pc, lr
76-
%tmp1 = load <2 x i32>, <2 x i32>* %A
77-
%tmp2 = load <2 x i32>, <2 x i32>* %B
78-
%tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 0, i32 2>
79-
%tmp4 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 3>
80-
%tmp5 = mul <2 x i32> %tmp3, %tmp4
81-
ret <2 x i32> %tmp5
76+
%tmp1 = load <2 x i32>, <2 x i32>* %A
77+
%tmp2 = load <2 x i32>, <2 x i32>* %B
78+
%tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 0, i32 2>
79+
%tmp4 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 3>
80+
%tmp5 = mul <2 x i32> %tmp3, %tmp4
81+
ret <2 x i32> %tmp5
8282
}
8383

8484
define <4 x i32> @vtrni32_Qres(<2 x i32>* %A, <2 x i32>* %B) nounwind {
@@ -90,10 +90,10 @@ define <4 x i32> @vtrni32_Qres(<2 x i32>* %A, <2 x i32>* %B) nounwind {
9090
; CHECK-NEXT: vmov r0, r1, [[LDR0]]
9191
; CHECK-NEXT: vmov r2, r3, [[LDR1]]
9292
; CHECK-NEXT: mov pc, lr
93-
%tmp1 = load <2 x i32>, <2 x i32>* %A
94-
%tmp2 = load <2 x i32>, <2 x i32>* %B
95-
%tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
96-
ret <4 x i32> %tmp3
93+
%tmp1 = load <2 x i32>, <2 x i32>* %A
94+
%tmp2 = load <2 x i32>, <2 x i32>* %B
95+
%tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
96+
ret <4 x i32> %tmp3
9797
}
9898

9999
define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind {
@@ -105,12 +105,12 @@ define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind {
105105
; CHECK-NEXT: vadd.f32 d16, d17, d16
106106
; CHECK-NEXT: vmov r0, r1, d16
107107
; CHECK-NEXT: mov pc, lr
108-
%tmp1 = load <2 x float>, <2 x float>* %A
109-
%tmp2 = load <2 x float>, <2 x float>* %B
110-
%tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 0, i32 2>
111-
%tmp4 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 1, i32 3>
112-
%tmp5 = fadd <2 x float> %tmp3, %tmp4
113-
ret <2 x float> %tmp5
108+
%tmp1 = load <2 x float>, <2 x float>* %A
109+
%tmp2 = load <2 x float>, <2 x float>* %B
110+
%tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 0, i32 2>
111+
%tmp4 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 1, i32 3>
112+
%tmp5 = fadd <2 x float> %tmp3, %tmp4
113+
ret <2 x float> %tmp5
114114
}
115115

116116
define <4 x float> @vtrnf_Qres(<2 x float>* %A, <2 x float>* %B) nounwind {
@@ -122,10 +122,10 @@ define <4 x float> @vtrnf_Qres(<2 x float>* %A, <2 x float>* %B) nounwind {
122122
; CHECK-NEXT: vmov r0, r1, [[LDR0]]
123123
; CHECK-NEXT: vmov r2, r3, [[LDR1]]
124124
; CHECK-NEXT: mov pc, lr
125-
%tmp1 = load <2 x float>, <2 x float>* %A
126-
%tmp2 = load <2 x float>, <2 x float>* %B
127-
%tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
128-
ret <4 x float> %tmp3
125+
%tmp1 = load <2 x float>, <2 x float>* %A
126+
%tmp2 = load <2 x float>, <2 x float>* %B
127+
%tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
128+
ret <4 x float> %tmp3
129129
}
130130

131131
define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
@@ -138,12 +138,12 @@ define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
138138
; CHECK-NEXT: vmov r0, r1, d16
139139
; CHECK-NEXT: vmov r2, r3, d17
140140
; CHECK-NEXT: mov pc, lr
141-
%tmp1 = load <16 x i8>, <16 x i8>* %A
142-
%tmp2 = load <16 x i8>, <16 x i8>* %B
143-
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>
144-
%tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31>
145-
%tmp5 = add <16 x i8> %tmp3, %tmp4
146-
ret <16 x i8> %tmp5
141+
%tmp1 = load <16 x i8>, <16 x i8>* %A
142+
%tmp2 = load <16 x i8>, <16 x i8>* %B
143+
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>
144+
%tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31>
145+
%tmp5 = add <16 x i8> %tmp3, %tmp4
146+
ret <16 x i8> %tmp5
147147
}
148148

149149
define <32 x i8> @vtrnQi8_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind {
@@ -155,10 +155,10 @@ define <32 x i8> @vtrnQi8_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind {
155155
; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]!
156156
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
157157
; CHECK-NEXT: mov pc, lr
158-
%tmp1 = load <16 x i8>, <16 x i8>* %A
159-
%tmp2 = load <16 x i8>, <16 x i8>* %B
160-
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <32 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30, i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31>
161-
ret <32 x i8> %tmp3
158+
%tmp1 = load <16 x i8>, <16 x i8>* %A
159+
%tmp2 = load <16 x i8>, <16 x i8>* %B
160+
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <32 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30, i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31>
161+
ret <32 x i8> %tmp3
162162
}
163163

164164
define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
@@ -171,12 +171,12 @@ define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
171171
; CHECK-NEXT: vmov r0, r1, d16
172172
; CHECK-NEXT: vmov r2, r3, d17
173173
; CHECK-NEXT: mov pc, lr
174-
%tmp1 = load <8 x i16>, <8 x i16>* %A
175-
%tmp2 = load <8 x i16>, <8 x i16>* %B
176-
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
177-
%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
178-
%tmp5 = add <8 x i16> %tmp3, %tmp4
179-
ret <8 x i16> %tmp5
174+
%tmp1 = load <8 x i16>, <8 x i16>* %A
175+
%tmp2 = load <8 x i16>, <8 x i16>* %B
176+
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
177+
%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
178+
%tmp5 = add <8 x i16> %tmp3, %tmp4
179+
ret <8 x i16> %tmp5
180180
}
181181

182182
define <16 x i16> @vtrnQi16_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind {
@@ -188,10 +188,10 @@ define <16 x i16> @vtrnQi16_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind {
188188
; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
189189
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
190190
; CHECK-NEXT: mov pc, lr
191-
%tmp1 = load <8 x i16>, <8 x i16>* %A
192-
%tmp2 = load <8 x i16>, <8 x i16>* %B
193-
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14, i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
194-
ret <16 x i16> %tmp3
191+
%tmp1 = load <8 x i16>, <8 x i16>* %A
192+
%tmp2 = load <8 x i16>, <8 x i16>* %B
193+
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14, i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
194+
ret <16 x i16> %tmp3
195195
}
196196

197197
define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
@@ -204,12 +204,12 @@ define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
204204
; CHECK-NEXT: vmov r0, r1, d16
205205
; CHECK-NEXT: vmov r2, r3, d17
206206
; CHECK-NEXT: mov pc, lr
207-
%tmp1 = load <4 x i32>, <4 x i32>* %A
208-
%tmp2 = load <4 x i32>, <4 x i32>* %B
209-
%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
210-
%tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
211-
%tmp5 = add <4 x i32> %tmp3, %tmp4
212-
ret <4 x i32> %tmp5
207+
%tmp1 = load <4 x i32>, <4 x i32>* %A
208+
%tmp2 = load <4 x i32>, <4 x i32>* %B
209+
%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
210+
%tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
211+
%tmp5 = add <4 x i32> %tmp3, %tmp4
212+
ret <4 x i32> %tmp5
213213
}
214214

215215
define <8 x i32> @vtrnQi32_QQres(<4 x i32>* %A, <4 x i32>* %B) nounwind {
@@ -221,10 +221,10 @@ define <8 x i32> @vtrnQi32_QQres(<4 x i32>* %A, <4 x i32>* %B) nounwind {
221221
; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
222222
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
223223
; CHECK-NEXT: mov pc, lr
224-
%tmp1 = load <4 x i32>, <4 x i32>* %A
225-
%tmp2 = load <4 x i32>, <4 x i32>* %B
226-
%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <8 x i32> <i32 0, i32 4, i32 2, i32 6, i32 1, i32 5, i32 3, i32 7>
227-
ret <8 x i32> %tmp3
224+
%tmp1 = load <4 x i32>, <4 x i32>* %A
225+
%tmp2 = load <4 x i32>, <4 x i32>* %B
226+
%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <8 x i32> <i32 0, i32 4, i32 2, i32 6, i32 1, i32 5, i32 3, i32 7>
227+
ret <8 x i32> %tmp3
228228
}
229229

230230
define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind {
@@ -237,12 +237,12 @@ define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind {
237237
; CHECK-NEXT: vmov r0, r1, d16
238238
; CHECK-NEXT: vmov r2, r3, d17
239239
; CHECK-NEXT: mov pc, lr
240-
%tmp1 = load <4 x float>, <4 x float>* %A
241-
%tmp2 = load <4 x float>, <4 x float>* %B
242-
%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
243-
%tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
244-
%tmp5 = fadd <4 x float> %tmp3, %tmp4
245-
ret <4 x float> %tmp5
240+
%tmp1 = load <4 x float>, <4 x float>* %A
241+
%tmp2 = load <4 x float>, <4 x float>* %B
242+
%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
243+
%tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
244+
%tmp5 = fadd <4 x float> %tmp3, %tmp4
245+
ret <4 x float> %tmp5
246246
}
247247

248248
define <8 x float> @vtrnQf_QQres(<4 x float>* %A, <4 x float>* %B) nounwind {
@@ -254,10 +254,10 @@ define <8 x float> @vtrnQf_QQres(<4 x float>* %A, <4 x float>* %B) nounwind {
254254
; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
255255
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
256256
; CHECK-NEXT: mov pc, lr
257-
%tmp1 = load <4 x float>, <4 x float>* %A
258-
%tmp2 = load <4 x float>, <4 x float>* %B
259-
%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <8 x i32> <i32 0, i32 4, i32 2, i32 6, i32 1, i32 5, i32 3, i32 7>
260-
ret <8 x float> %tmp3
257+
%tmp1 = load <4 x float>, <4 x float>* %A
258+
%tmp2 = load <4 x float>, <4 x float>* %B
259+
%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <8 x i32> <i32 0, i32 4, i32 2, i32 6, i32 1, i32 5, i32 3, i32 7>
260+
ret <8 x float> %tmp3
261261
}
262262

263263

@@ -270,12 +270,12 @@ define <8 x i8> @vtrni8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
270270
; CHECK-NEXT: vadd.i8 d16, d17, d16
271271
; CHECK-NEXT: vmov r0, r1, d16
272272
; CHECK-NEXT: mov pc, lr
273-
%tmp1 = load <8 x i8>, <8 x i8>* %A
274-
%tmp2 = load <8 x i8>, <8 x i8>* %B
275-
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 2, i32 10, i32 undef, i32 12, i32 6, i32 14>
276-
%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 undef, i32 undef, i32 15>
277-
%tmp5 = add <8 x i8> %tmp3, %tmp4
278-
ret <8 x i8> %tmp5
273+
%tmp1 = load <8 x i8>, <8 x i8>* %A
274+
%tmp2 = load <8 x i8>, <8 x i8>* %B
275+
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 2, i32 10, i32 undef, i32 12, i32 6, i32 14>
276+
%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 undef, i32 undef, i32 15>
277+
%tmp5 = add <8 x i8> %tmp3, %tmp4
278+
ret <8 x i8> %tmp5
279279
}
280280

281281
define <16 x i8> @vtrni8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
@@ -287,10 +287,10 @@ define <16 x i8> @vtrni8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
287287
; CHECK-NEXT: vmov r0, r1, [[LDR0]]
288288
; CHECK-NEXT: vmov r2, r3, [[LDR1]]
289289
; CHECK-NEXT: mov pc, lr
290-
%tmp1 = load <8 x i8>, <8 x i8>* %A
291-
%tmp2 = load <8 x i8>, <8 x i8>* %B
292-
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 undef, i32 2, i32 10, i32 undef, i32 12, i32 6, i32 14, i32 1, i32 9, i32 3, i32 11, i32 5, i32 undef, i32 undef, i32 15>
293-
ret <16 x i8> %tmp3
290+
%tmp1 = load <8 x i8>, <8 x i8>* %A
291+
%tmp2 = load <8 x i8>, <8 x i8>* %B
292+
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 undef, i32 2, i32 10, i32 undef, i32 12, i32 6, i32 14, i32 1, i32 9, i32 3, i32 11, i32 5, i32 undef, i32 undef, i32 15>
293+
ret <16 x i8> %tmp3
294294
}
295295

296296
define <8 x i16> @vtrnQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
@@ -303,12 +303,12 @@ define <8 x i16> @vtrnQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
303303
; CHECK-NEXT: vmov r0, r1, d16
304304
; CHECK-NEXT: vmov r2, r3, d17
305305
; CHECK-NEXT: mov pc, lr
306-
%tmp1 = load <8 x i16>, <8 x i16>* %A
307-
%tmp2 = load <8 x i16>, <8 x i16>* %B
308-
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 undef, i32 undef, i32 4, i32 12, i32 6, i32 14>
309-
%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 undef, i32 3, i32 11, i32 5, i32 13, i32 undef, i32 undef>
310-
%tmp5 = add <8 x i16> %tmp3, %tmp4
311-
ret <8 x i16> %tmp5
306+
%tmp1 = load <8 x i16>, <8 x i16>* %A
307+
%tmp2 = load <8 x i16>, <8 x i16>* %B
308+
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 undef, i32 undef, i32 4, i32 12, i32 6, i32 14>
309+
%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 undef, i32 3, i32 11, i32 5, i32 13, i32 undef, i32 undef>
310+
%tmp5 = add <8 x i16> %tmp3, %tmp4
311+
ret <8 x i16> %tmp5
312312
}
313313

314314
define <16 x i16> @vtrnQi16_undef_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind {
@@ -320,10 +320,10 @@ define <16 x i16> @vtrnQi16_undef_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind {
320320
; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
321321
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
322322
; CHECK-NEXT: mov pc, lr
323-
%tmp1 = load <8 x i16>, <8 x i16>* %A
324-
%tmp2 = load <8 x i16>, <8 x i16>* %B
325-
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 8, i32 undef, i32 undef, i32 4, i32 12, i32 6, i32 14, i32 1, i32 undef, i32 3, i32 11, i32 5, i32 13, i32 undef, i32 undef>
326-
ret <16 x i16> %tmp3
323+
%tmp1 = load <8 x i16>, <8 x i16>* %A
324+
%tmp2 = load <8 x i16>, <8 x i16>* %B
325+
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 8, i32 undef, i32 undef, i32 4, i32 12, i32 6, i32 14, i32 1, i32 undef, i32 3, i32 11, i32 5, i32 13, i32 undef, i32 undef>
326+
ret <16 x i16> %tmp3
327327
}
328328

329329
define <8 x i16> @vtrn_lower_shufflemask_undef(<4 x i16>* %A, <4 x i16>* %B) {

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