Skip to content
This repository was archived by the owner on Feb 5, 2019. It is now read-only.

Commit 498863b

Browse files
zmodemzmodem
committed
Merging r309495:
------------------------------------------------------------------------ r309495 | fhahn | 2017-07-29 13:35:28 -0700 (Sat, 29 Jul 2017) | 30 lines [AArch64] Tie source and destination operands for AESMC/AESIMC. Summary: Most CPUs implementing AES fusion require instruction pairs of the form AESE Vn, _ AESMC Vn, Vn and AESD Vn, _ AESIMC Vn, Vn The constraint is added to AES(I)MC instructions which use the result of an AES(E|D) instruction by using AES(I)MCTrr pseudo instructions, which constraint source and destination registers to be the same. A nice side effect of this change is that now all possible pairs are scheduled back-to-back on the exynos-m1 for the misched-fusion-aes.ll test case. I had to update aes_load_store. The version I added initially was very reduced and with the new constraint, AESE/AESMC could not be scheduled back-to-back. I updated the test to be more realistic and still expose the same scheduling problem as the initial test case. Reviewers: t.p.northover, rengolin, evandro, kristof.beyls, silviu.baranga Reviewed By: t.p.northover, evandro Subscribers: aemerson, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D35299 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@309765 91177308-0d34-0410-b5e6-96231b3b80d8
1 parent b20d324 commit 498863b

File tree

5 files changed

+91
-84
lines changed

5 files changed

+91
-84
lines changed

‎lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -946,6 +946,18 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
946946
case AArch64::CMP_SWAP_128:
947947
return expandCMP_SWAP_128(MBB, MBBI, NextMBBI);
948948

949+
case AArch64::AESMCrrTied:
950+
case AArch64::AESIMCrrTied: {
951+
MachineInstrBuilder MIB =
952+
BuildMI(MBB, MBBI, MI.getDebugLoc(),
953+
TII->get(Opcode == AArch64::AESMCrrTied ? AArch64::AESMCrr :
954+
AArch64::AESIMCrr))
955+
.add(MI.getOperand(0))
956+
.add(MI.getOperand(1));
957+
transferImpOps(MI, MIB, MIB);
958+
MI.eraseFromParent();
959+
return true;
960+
}
949961
}
950962
return false;
951963
}

‎lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,9 @@ def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">,
3737
AssemblerPredicate<"FeatureFullFP16", "fullfp16">;
3838
def HasSPE : Predicate<"Subtarget->hasSPE()">,
3939
AssemblerPredicate<"FeatureSPE", "spe">;
40+
def HasFuseAES : Predicate<"Subtarget->hasFuseAES()">,
41+
AssemblerPredicate<"FeatureFuseAES",
42+
"fuse-aes">;
4043
def HasSVE : Predicate<"Subtarget->hasSVE()">,
4144
AssemblerPredicate<"FeatureSVE", "sve">;
4245

@@ -5304,6 +5307,31 @@ def AESDrr : AESTiedInst<0b0101, "aesd", int_aarch64_crypto_aesd>;
53045307
def AESMCrr : AESInst< 0b0110, "aesmc", int_aarch64_crypto_aesmc>;
53055308
def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>;
53065309

5310+
// Pseudo instructions for AESMCrr/AESIMCrr with a register constraint required
5311+
// for AES fusion on some CPUs.
5312+
let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in {
5313+
def AESMCrrTied: Pseudo<(outs V128:$Rd), (ins V128:$Rn), [], "$Rn = $Rd">,
5314+
Sched<[WriteV]>;
5315+
def AESIMCrrTied: Pseudo<(outs V128:$Rd), (ins V128:$Rn), [], "$Rn = $Rd">,
5316+
Sched<[WriteV]>;
5317+
}
5318+
5319+
// Only use constrained versions of AES(I)MC instructions if they are paired with
5320+
// AESE/AESD.
5321+
def : Pat<(v16i8 (int_aarch64_crypto_aesmc
5322+
(v16i8 (int_aarch64_crypto_aese (v16i8 V128:$src1),
5323+
(v16i8 V128:$src2))))),
5324+
(v16i8 (AESMCrrTied (v16i8 (AESErr (v16i8 V128:$src1),
5325+
(v16i8 V128:$src2)))))>,
5326+
Requires<[HasFuseAES]>;
5327+
5328+
def : Pat<(v16i8 (int_aarch64_crypto_aesimc
5329+
(v16i8 (int_aarch64_crypto_aesd (v16i8 V128:$src1),
5330+
(v16i8 V128:$src2))))),
5331+
(v16i8 (AESIMCrrTied (v16i8 (AESDrr (v16i8 V128:$src1),
5332+
(v16i8 V128:$src2)))))>,
5333+
Requires<[HasFuseAES]>;
5334+
53075335
def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_aarch64_crypto_sha1c>;
53085336
def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_aarch64_crypto_sha1p>;
53095337
def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_aarch64_crypto_sha1m>;

‎lib/Target/AArch64/AArch64MacroFusion.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -118,11 +118,13 @@ static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
118118
// Fuse AES crypto operations.
119119
switch(SecondOpcode) {
120120
// AES encode.
121-
case AArch64::AESMCrr :
121+
case AArch64::AESMCrr:
122+
case AArch64::AESMCrrTied:
122123
return FirstOpcode == AArch64::AESErr ||
123124
FirstOpcode == AArch64::INSTRUCTION_LIST_END;
124125
// AES decode.
125126
case AArch64::AESIMCrr:
127+
case AArch64::AESIMCrrTied:
126128
return FirstOpcode == AArch64::AESDrr ||
127129
FirstOpcode == AArch64::INSTRUCTION_LIST_END;
128130
}

‎test/CodeGen/AArch64/misched-fusion-aes.ll

Lines changed: 47 additions & 83 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,10 @@
1-
; RUN: llc %s -o - -mtriple=aarch64-unknown -mattr=+fuse-aes,+crypto | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSEALLPAIRS
2-
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=generic -mattr=+crypto | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSEALLPAIRS
3-
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a53 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSEALLPAIRS
4-
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a57 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSEALLPAIRS
5-
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a72 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSEALLPAIRS
6-
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a73 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSEALLPAIRS
7-
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKM1
1+
; RUN: llc %s -o - -mtriple=aarch64-unknown -mattr=+fuse-aes,+crypto | FileCheck %s
2+
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=generic -mattr=+crypto | FileCheck %s
3+
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a53 | FileCheck %s
4+
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a57 | FileCheck %s
5+
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a72 | FileCheck %s
6+
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a73 | FileCheck %s
7+
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m1 | FileCheck %s
88

99
declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %d, <16 x i8> %k)
1010
declare <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %d)
@@ -76,41 +76,23 @@ define void @aesea(<16 x i8>* %a0, <16 x i8>* %b0, <16 x i8>* %c0, <16 x i8> %d,
7676
ret void
7777

7878
; CHECK-LABEL: aesea:
79-
; CHECKFUSEALLPAIRS: aese [[VA:v[0-7].16b]], {{v[0-7].16b}}
80-
; CHECKFUSEALLPAIRS-NEXT: aesmc {{v[0-7].16b}}, [[VA]]
81-
; CHECKFUSEALLPAIRS: aese [[VB:v[0-7].16b]], {{v[0-7].16b}}
82-
; CHECKFUSEALLPAIRS-NEXT: aesmc {{v[0-7].16b}}, [[VB]]
83-
; CHECKFUSEALLPAIRS: aese [[VC:v[0-7].16b]], {{v[0-7].16b}}
84-
; CHECKFUSEALLPAIRS-NEXT: aesmc {{v[0-7].16b}}, [[VC]]
85-
; CHECKFUSEALLPAIRS: aese [[VD:v[0-7].16b]], {{v[0-7].16b}}
86-
; CHECKFUSEALLPAIRS-NEXT: aesmc {{v[0-7].16b}}, [[VD]]
87-
; CHECKFUSEALLPAIRS: aese [[VE:v[0-7].16b]], {{v[0-7].16b}}
88-
; CHECKFUSEALLPAIRS-NEXT: aesmc {{v[0-7].16b}}, [[VE]]
89-
; CHECKFUSEALLPAIRS: aese [[VF:v[0-7].16b]], {{v[0-7].16b}}
90-
; CHECKFUSEALLPAIRS-NEXT: aesmc {{v[0-7].16b}}, [[VF]]
91-
; CHECKFUSEALLPAIRS: aese [[VG:v[0-7].16b]], {{v[0-7].16b}}
92-
; CHECKFUSEALLPAIRS-NEXT: aesmc {{v[0-7].16b}}, [[VG]]
93-
; CHECKFUSEALLPAIRS: aese [[VH:v[0-7].16b]], {{v[0-7].16b}}
94-
; CHECKFUSEALLPAIRS-NEXT: aesmc {{v[0-7].16b}}, [[VH]]
95-
; CHECKFUSEALLPAIRS-NOT: aesmc
96-
97-
; CHECKM1: aese [[VA:v[0-7].16b]], {{v[0-7].16b}}
98-
; CHECKM1-NEXT: aesmc {{v[0-7].16b}}, [[VA]]
99-
; CHECKM1: aese [[VH:v[0-7].16b]], {{v[0-7].16b}}
100-
; CHECKM1: aese [[VB:v[0-7].16b]], {{v[0-7].16b}}
101-
; CHECKM1-NEXT: aesmc {{v[0-7].16b}}, [[VB]]
102-
; CHECKM1: aese {{v[0-7].16b}}, {{v[0-7].16b}}
103-
; CHECKM1: aese [[VC:v[0-7].16b]], {{v[0-7].16b}}
104-
; CHECKM1-NEXT: aesmc {{v[0-7].16b}}, [[VC]]
105-
; CHECKM1: aese [[VD:v[0-7].16b]], {{v[0-7].16b}}
106-
; CHECKM1-NEXT: aesmc {{v[0-7].16b}}, [[VD]]
107-
; CHECKM1: aesmc {{v[0-7].16b}}, [[VH]]
108-
; CHECKM1: aese [[VE:v[0-7].16b]], {{v[0-7].16b}}
109-
; CHECKM1-NEXT: aesmc {{v[0-7].16b}}, [[VE]]
110-
; CHECKM1: aese [[VF:v[0-7].16b]], {{v[0-7].16b}}
111-
; CHECKM1-NEXT: aesmc {{v[0-7].16b}}, [[VF]]
112-
; CHECKM1: aese [[VG:v[0-7].16b]], {{v[0-7].16b}}
113-
; CHECKM1-NEXT: aesmc {{v[0-7].16b}}, [[VG]]
79+
; CHECK: aese [[VA:v[0-7].16b]], {{v[0-7].16b}}
80+
; CHECK-NEXT: aesmc [[VA]], [[VA]]
81+
; CHECK: aese [[VB:v[0-7].16b]], {{v[0-7].16b}}
82+
; CHECK-NEXT: aesmc [[VB]], [[VB]]
83+
; CHECK: aese [[VC:v[0-7].16b]], {{v[0-7].16b}}
84+
; CHECK-NEXT: aesmc [[VC]], [[VC]]
85+
; CHECK: aese [[VD:v[0-7].16b]], {{v[0-7].16b}}
86+
; CHECK-NEXT: aesmc [[VD]], [[VD]]
87+
; CHECK: aese [[VE:v[0-7].16b]], {{v[0-7].16b}}
88+
; CHECK-NEXT: aesmc [[VE]], [[VE]]
89+
; CHECK: aese [[VF:v[0-7].16b]], {{v[0-7].16b}}
90+
; CHECK-NEXT: aesmc [[VF]], [[VF]]
91+
; CHECK: aese [[VG:v[0-7].16b]], {{v[0-7].16b}}
92+
; CHECK-NEXT: aesmc [[VG]], [[VG]]
93+
; CHECK: aese [[VH:v[0-7].16b]], {{v[0-7].16b}}
94+
; CHECK-NEXT: aesmc [[VH]], [[VH]]
95+
; CHECK-NOT: aesmc
11496
}
11597

11698
define void @aesda(<16 x i8>* %a0, <16 x i8>* %b0, <16 x i8>* %c0, <16 x i8> %d, <16 x i8> %e) {
@@ -178,41 +160,23 @@ define void @aesda(<16 x i8>* %a0, <16 x i8>* %b0, <16 x i8>* %c0, <16 x i8> %d,
178160
ret void
179161

180162
; CHECK-LABEL: aesda:
181-
; CHECKFUSEALLPAIRS: aesd [[VA:v[0-7].16b]], {{v[0-7].16b}}
182-
; CHECKFUSEALLPAIRS-NEXT: aesimc {{v[0-7].16b}}, [[VA]]
183-
; CHECKFUSEALLPAIRS: aesd [[VB:v[0-7].16b]], {{v[0-7].16b}}
184-
; CHECKFUSEALLPAIRS-NEXT: aesimc {{v[0-7].16b}}, [[VB]]
185-
; CHECKFUSEALLPAIRS: aesd [[VC:v[0-7].16b]], {{v[0-7].16b}}
186-
; CHECKFUSEALLPAIRS-NEXT: aesimc {{v[0-7].16b}}, [[VC]]
187-
; CHECKFUSEALLPAIRS: aesd [[VD:v[0-7].16b]], {{v[0-7].16b}}
188-
; CHECKFUSEALLPAIRS-NEXT: aesimc {{v[0-7].16b}}, [[VD]]
189-
; CHECKFUSEALLPAIRS: aesd [[VE:v[0-7].16b]], {{v[0-7].16b}}
190-
; CHECKFUSEALLPAIRS-NEXT: aesimc {{v[0-7].16b}}, [[VE]]
191-
; CHECKFUSEALLPAIRS: aesd [[VF:v[0-7].16b]], {{v[0-7].16b}}
192-
; CHECKFUSEALLPAIRS-NEXT: aesimc {{v[0-7].16b}}, [[VF]]
193-
; CHECKFUSEALLPAIRS: aesd [[VG:v[0-7].16b]], {{v[0-7].16b}}
194-
; CHECKFUSEALLPAIRS-NEXT: aesimc {{v[0-7].16b}}, [[VG]]
195-
; CHECKFUSEALLPAIRS: aesd [[VH:v[0-7].16b]], {{v[0-7].16b}}
196-
; CHECKFUSEALLPAIRS-NEXT: aesimc {{v[0-7].16b}}, [[VH]]
197-
; CHECKFUSEALLPAIRS-NOT: aesimc
198-
199-
; CHECKM1: aesd [[VA:v[0-7].16b]], {{v[0-7].16b}}
200-
; CHECKM1-NEXT: aesimc {{v[0-7].16b}}, [[VA]]
201-
; CHECKM1: aesd [[VH:v[0-7].16b]], {{v[0-7].16b}}
202-
; CHECKM1: aesd [[VB:v[0-7].16b]], {{v[0-7].16b}}
203-
; CHECKM1-NEXT: aesimc {{v[0-7].16b}}, [[VB]]
204-
; CHECKM1: aesd {{v[0-7].16b}}, {{v[0-7].16b}}
205-
; CHECKM1: aesd [[VC:v[0-7].16b]], {{v[0-7].16b}}
206-
; CHECKM1-NEXT: aesimc {{v[0-7].16b}}, [[VC]]
207-
; CHECKM1: aesd [[VD:v[0-7].16b]], {{v[0-7].16b}}
208-
; CHECKM1-NEXT: aesimc {{v[0-7].16b}}, [[VD]]
209-
; CHECKM1: aesimc {{v[0-7].16b}}, [[VH]]
210-
; CHECKM1: aesd [[VE:v[0-7].16b]], {{v[0-7].16b}}
211-
; CHECKM1-NEXT: aesimc {{v[0-7].16b}}, [[VE]]
212-
; CHECKM1: aesd [[VF:v[0-7].16b]], {{v[0-7].16b}}
213-
; CHECKM1-NEXT: aesimc {{v[0-7].16b}}, [[VF]]
214-
; CHECKM1: aesd [[VG:v[0-7].16b]], {{v[0-7].16b}}
215-
; CHECKM1-NEXT: aesimc {{v[0-7].16b}}, [[VG]]
163+
; CHECK: aesd [[VA:v[0-7].16b]], {{v[0-7].16b}}
164+
; CHECK-NEXT: aesimc [[VA]], [[VA]]
165+
; CHECK: aesd [[VB:v[0-7].16b]], {{v[0-7].16b}}
166+
; CHECK-NEXT: aesimc [[VB]], [[VB]]
167+
; CHECK: aesd [[VC:v[0-7].16b]], {{v[0-7].16b}}
168+
; CHECK-NEXT: aesimc [[VC]], [[VC]]
169+
; CHECK: aesd [[VD:v[0-7].16b]], {{v[0-7].16b}}
170+
; CHECK-NEXT: aesimc [[VD]], [[VD]]
171+
; CHECK: aesd [[VE:v[0-7].16b]], {{v[0-7].16b}}
172+
; CHECK-NEXT: aesimc [[VE]], [[VE]]
173+
; CHECK: aesd [[VF:v[0-7].16b]], {{v[0-7].16b}}
174+
; CHECK-NEXT: aesimc [[VF]], [[VF]]
175+
; CHECK: aesd [[VG:v[0-7].16b]], {{v[0-7].16b}}
176+
; CHECK-NEXT: aesimc [[VG]], [[VG]]
177+
; CHECK: aesd [[VH:v[0-7].16b]], {{v[0-7].16b}}
178+
; CHECK-NEXT: aesimc [[VH]], [[VH]]
179+
; CHECK-NOT: aesimc
216180
}
217181

218182
define void @aes_load_store(<16 x i8> *%p1, <16 x i8> *%p2 , <16 x i8> *%p3) {
@@ -225,20 +189,20 @@ entry:
225189
%in1 = load <16 x i8>, <16 x i8>* %p1, align 16
226190
store <16 x i8> %in1, <16 x i8>* %x1, align 16
227191
%aese1 = call <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %in1, <16 x i8> %in1) #2
228-
store <16 x i8> %aese1, <16 x i8>* %x2, align 16
229192
%in2 = load <16 x i8>, <16 x i8>* %p2, align 16
230193
%aesmc1= call <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %aese1) #2
231-
store <16 x i8> %aesmc1, <16 x i8>* %x3, align 16
232194
%aese2 = call <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %in1, <16 x i8> %in2) #2
233-
store <16 x i8> %aese2, <16 x i8>* %x4, align 16
195+
store <16 x i8> %aesmc1, <16 x i8>* %x3, align 16
196+
%in3 = load <16 x i8>, <16 x i8>* %p3, align 16
234197
%aesmc2= call <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %aese2) #2
235-
store <16 x i8> %aesmc2, <16 x i8>* %x5, align 16
198+
%aese3 = call <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %aesmc2, <16 x i8> %in3) #2
199+
store <16 x i8> %aese3, <16 x i8>* %x5, align 16
236200
ret void
237201

238202
; CHECK-LABEL: aes_load_store:
239203
; CHECK: aese [[VA:v[0-7].16b]], {{v[0-7].16b}}
240-
; CHECK-NEXT: aesmc {{v[0-7].16b}}, [[VA]]
204+
; CHECK-NEXT: aesmc [[VA]], [[VA]]
241205
; CHECK: aese [[VB:v[0-7].16b]], {{v[0-7].16b}}
242-
; CHECK-NEXT: aesmc {{v[0-7].16b}}, [[VB]]
206+
; CHECK-NEXT: aesmc [[VB]], [[VB]]
243207
; CHECK-NOT: aesmc
244208
}

‎test/MC/AArch64/arm64-crypto.s

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
; RUN: llvm-mc -triple arm64-apple-darwin -mattr=crypto -show-encoding -output-asm-variant=1 < %s | FileCheck %s
2+
; RUN: llvm-mc -triple arm64-apple-darwin -mattr='+crypto,+fuse-aes' -show-encoding -output-asm-variant=1 < %s | FileCheck %s
23

34
foo:
45
aese.16b v0, v1

0 commit comments

Comments
 (0)