[Hexagon] Fix a condition in HexagonEarlyIfConv.cpp

Krzysztof Parzyszek · Krzysztof Parzyszek · commit 702396c9dc87 · 2017-03-14T15:21:33.000Z
This fixes llvm.org/PR32265. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297745 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
@@ -482,7 +482,7 @@ unsigned HexagonEarlyIfConversion::computePhiCost(const MachineBasicBlock *B,
     const MachineOperand &RB = MI.getOperand(3);
     assert(RA.isReg() && RB.isReg());
     // Must have a MUX if the phi uses a subregister.
-    if (RA.getSubReg() != 0 || RA.getSubReg() != 0) {
+    if (RA.getSubReg() != 0 || RB.getSubReg() != 0) {
       Cost++;
       continue;
     }

Original file line number	Diff line number	Diff line change
`@@ -482,7 +482,7 @@ unsigned HexagonEarlyIfConversion::computePhiCost(const MachineBasicBlock *B,`
`482`	`482`	`const MachineOperand &RB = MI.getOperand(3);`
`483`	`483`	`assert(RA.isReg() && RB.isReg());`
`484`	`484`	`// Must have a MUX if the phi uses a subregister.`
`485`		`- if (RA.getSubReg() != 0 \|\| RA.getSubReg() != 0) {`
	`485`	`+ if (RA.getSubReg() != 0 \|\| RB.getSubReg() != 0) {`
`486`	`486`	`Cost++;`
`487`	`487`	`continue;`
`488`	`488`	`}`