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James Molloyarielb1
James Molloy
authored and
arielb1
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TBB generation: spot redefinitions of index register
We match a sequence of 3-4 instructions into a tTBB pseudo. One of our checks is that a particular register in that sequence is killed (so it can be clobbered by the pseudo). We weren't noticing if an errant MOV or other instruction had infiltrated the sequence we were walking. If it had, and it defined the register we've already identified as killed, it makes it live across the tBR_JT and thus unclobberable. Notice this case and bail out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294949 91177308-0d34-0410-b5e6-96231b3b80d8
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‎lib/Target/ARM/ARMConstantIslandPass.cpp

Lines changed: 17 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1984,6 +1984,16 @@ static bool jumpTableFollowsTB(MachineInstr *JTMI, MachineInstr *CPEMI) {
19841984
&*MBB->begin() == CPEMI;
19851985
}
19861986

1987+
static bool registerDefinedBetween(unsigned Reg,
1988+
MachineBasicBlock::iterator From,
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MachineBasicBlock::iterator To,
1990+
const TargetRegisterInfo *TRI) {
1991+
for (auto I = From; I != To; ++I)
1992+
if (I->modifiesRegister(Reg, TRI))
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return true;
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return false;
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}
1996+
19871997
/// optimizeThumb2JumpTables - Use tbb / tbh instructions to generate smaller
19881998
/// jumptables when it's possible.
19891999
bool ARMConstantIslands::optimizeThumb2JumpTables() {
@@ -2076,6 +2086,7 @@ bool ARMConstantIslands::optimizeThumb2JumpTables() {
20762086
continue;
20772087

20782088
// If we're in PIC mode, there should be another ADD following.
2089+
auto *TRI = STI->getRegisterInfo();
20792090
if (isPositionIndependentOrROPI) {
20802091
MachineInstr *Add = Load->getNextNode();
20812092
if (Add->getOpcode() != ARM::tADDrr ||
@@ -2085,12 +2096,17 @@ bool ARMConstantIslands::optimizeThumb2JumpTables() {
20852096
continue;
20862097
if (Add->getOperand(0).getReg() != MI->getOperand(0).getReg())
20872098
continue;
2088-
2099+
if (registerDefinedBetween(IdxReg, Add->getNextNode(), MI, TRI))
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// IdxReg gets redefined in the middle of the sequence.
2101+
continue;
20892102
Add->eraseFromParent();
20902103
DeadSize += 2;
20912104
} else {
20922105
if (Load->getOperand(0).getReg() != MI->getOperand(0).getReg())
20932106
continue;
2107+
if (registerDefinedBetween(IdxReg, Load->getNextNode(), MI, TRI))
2108+
// IdxReg gets redefined in the middle of the sequence.
2109+
continue;
20942110
}
20952111

20962112

‎test/CodeGen/Thumb/tbb-reuse.mir

Lines changed: 151 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,151 @@
1+
# RUN: llc -run-pass arm-cp-islands %s -o - | FileCheck %s
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--- |
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; ModuleID = '<stdin>'
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source_filename = "<stdin>"
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv6m--none-eabi"
8+
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declare void @exit0()
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declare void @exit1(i32)
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declare void @exit2()
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declare void @exit3()
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declare void @exit4()
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define void @jump_table(i32 %val, i32 %arg2, i32 %arg3, i32 %arg4) {
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entry:
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switch i32 %val, label %default [
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i32 1, label %lab1
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i32 2, label %lab2
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i32 3, label %lab3
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i32 4, label %lab4
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]
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default: ; preds = %entry
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tail call void @exit0()
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ret void
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lab1: ; preds = %entry
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%b = sub i32 %val, 1
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%a = shl i32 %b, 2
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tail call void @exit1(i32 %a)
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ret void
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lab2: ; preds = %entry
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tail call void @exit2()
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ret void
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lab3: ; preds = %entry
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tail call void @exit3()
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ret void
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lab4: ; preds = %entry
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tail call void @exit4()
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ret void
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}
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; Function Attrs: nounwind
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declare void @llvm.stackprotector(i8*, i8**) #0
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attributes #0 = { nounwind }
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56+
...
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---
58+
name: jump_table
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alignment: 1
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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liveins:
66+
- { reg: '%r0' }
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calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13',
68+
'%d14', '%d15', '%q4', '%q5', '%q6', '%q7', '%r4',
69+
'%r5', '%r6', '%r7', '%r8', '%r9', '%r10', '%r11',
70+
'%s16', '%s17', '%s18', '%s19', '%s20', '%s21',
71+
'%s22', '%s23', '%s24', '%s25', '%s26', '%s27',
72+
'%s28', '%s29', '%s30', '%s31', '%d8_d10', '%d9_d11',
73+
'%d10_d12', '%d11_d13', '%d12_d14', '%d13_d15',
74+
'%q4_q5', '%q5_q6', '%q6_q7', '%q4_q5_q6_q7', '%r4_r5',
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'%r6_r7', '%r8_r9', '%r10_r11', '%d8_d9_d10', '%d9_d10_d11',
76+
'%d10_d11_d12', '%d11_d12_d13', '%d12_d13_d14',
77+
'%d13_d14_d15', '%d8_d10_d12', '%d9_d11_d13', '%d10_d12_d14',
78+
'%d11_d13_d15', '%d8_d10_d12_d14', '%d9_d11_d13_d15',
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'%d9_d10', '%d11_d12', '%d13_d14', '%d9_d10_d11_d12',
80+
'%d11_d12_d13_d14' ]
81+
frameInfo:
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isFrameAddressTaken: false
83+
isReturnAddressTaken: false
84+
hasStackMap: false
85+
hasPatchPoint: false
86+
stackSize: 8
87+
offsetAdjustment: 0
88+
maxAlignment: 4
89+
adjustsStack: true
90+
hasCalls: true
91+
maxCallFrameSize: 0
92+
hasOpaqueSPAdjustment: false
93+
hasVAStart: false
94+
hasMustTailInVarArgFunc: false
95+
stack:
96+
- { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr' }
97+
- { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r7' }
98+
jumpTable:
99+
kind: inline
100+
entries:
101+
- id: 0
102+
blocks: [ '%bb.3.lab1', '%bb.4.lab2', '%bb.5.lab3', '%bb.6.lab4' ]
103+
# r1 is redefined in the middle of the recognizable jump sequence - it shouldn't be clobbered!
104+
# CHECK-NOT: tTBB_JT
105+
106+
body: |
107+
bb.0.entry:
108+
successors: %bb.2.default(0x19999998), %bb.1.entry(0x66666668)
109+
liveins: %r0, %r7, %lr
110+
111+
frame-setup tPUSH 14, _, killed %r7, killed %lr, implicit-def %sp, implicit %sp
112+
frame-setup CFI_INSTRUCTION def_cfa_offset 8
113+
frame-setup CFI_INSTRUCTION offset %lr, -4
114+
frame-setup CFI_INSTRUCTION offset %r7, -8
115+
%r1, dead %cpsr = tSUBi3 %r0, 1, 14, _
116+
tCMPi8 %r1, 3, 14, _, implicit-def %cpsr
117+
tBcc %bb.2.default, 8, killed %cpsr
118+
119+
bb.1.entry:
120+
successors: %bb.3.lab1(0x20000000), %bb.4.lab2(0x20000000), %bb.5.lab3(0x20000000), %bb.6.lab4(0x20000000)
121+
liveins: %r0, %r1
122+
123+
%r1, dead %cpsr = tLSLri killed %r1, 2, 14, _
124+
%r2 = tLEApcrelJT %jump-table.0, 14, _
125+
%r2 = tLDRr killed %r1, killed %r2, 14, _ :: (load 4 from jump-table)
126+
%r1, dead %cpsr = tLSLri %r2, 2, 14, _
127+
tBR_JTr killed %r2, %jump-table.0
128+
129+
bb.2.default:
130+
tBL 14, _, @exit0, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp
131+
tPOP_RET 14, _, def %r7, def %pc, implicit-def %sp, implicit %sp
132+
133+
bb.3.lab1:
134+
liveins: %r0,%r1
135+
136+
tBL 14, _, @exit1, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit-def %sp
137+
tPOP_RET 14, _, def %r7, def %pc, implicit-def %sp, implicit %sp
138+
139+
bb.4.lab2:
140+
tBL 14, _, @exit2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp
141+
tPOP_RET 14, _, def %r7, def %pc, implicit-def %sp, implicit %sp
142+
143+
bb.5.lab3:
144+
tBL 14, _, @exit3, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp
145+
tPOP_RET 14, _, def %r7, def %pc, implicit-def %sp, implicit %sp
146+
147+
bb.6.lab4:
148+
tBL 14, _, @exit4, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp
149+
tPOP_RET 14, _, def %r7, def %pc, implicit-def %sp, implicit %sp
150+
151+
...

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