[InstCombine] Add constant vector support for X udiv C, where C >= signbit

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324728 91177308-0d34-0410-b5e6-96231b3b80d8

Author: RKSimon

lib/Transforms/InstCombine/InstCombineMulDivRem.cpp

@@ -1067,8 +1067,7 @@ static Instruction *foldUDivPow2Cst(Value *Op0, Value *Op1,
 // X udiv C, where C >= signbit
 static Instruction *foldUDivNegCst(Value *Op0, Value *Op1,
                                    const BinaryOperator &I, InstCombiner &IC) {
-  Value *ICI = IC.Builder.CreateICmpULT(Op0, cast<ConstantInt>(Op1));
-
+  Value *ICI = IC.Builder.CreateICmpULT(Op0, cast<Constant>(Op1));
   return SelectInst::Create(ICI, Constant::getNullValue(I.getType()),
                             ConstantInt::get(I.getType(), 1));
 }
@@ -1111,12 +1110,11 @@ static size_t visitUDivOperand(Value *Op0, Value *Op1, const BinaryOperator &I,
     return Actions.size();
   }
 
-  if (ConstantInt *C = dyn_cast<ConstantInt>(Op1))
-    // X udiv C, where C >= signbit
-    if (C->getValue().isNegative()) {
-      Actions.push_back(UDivFoldAction(foldUDivNegCst, C));
-      return Actions.size();
-    }
+  // X udiv C, where C >= signbit
+  if (match(Op1, m_Negative())) {
+    Actions.push_back(UDivFoldAction(foldUDivNegCst, Op1));
+    return Actions.size();
+  }
 
   // X udiv (C1 << N), where C1 is "1<<C2"  -->  X >> (N+C2)
   if (match(Op1, m_Shl(m_Power2(), m_Value())) ||

test/Transforms/InstCombine/udiv_select_to_select_shift.ll

@@ -24,7 +24,8 @@ define i64 @test(i64 %X, i1 %Cond ) {
 
 define <2 x i32> @PR34856(<2 x i32> %t0, <2 x i32> %t1) {
 ; CHECK-LABEL: @PR34856(
-; CHECK-NEXT:    [[DIV1:%.*]] = udiv <2 x i32> [[T1:%.*]], <i32 -7, i32 -7>
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt <2 x i32> [[T1:%.*]], <i32 -8, i32 -8>
+; CHECK-NEXT:    [[DIV1:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i32>
 ; CHECK-NEXT:    ret <2 x i32> [[DIV1]]
 ;
   %cmp = icmp eq <2 x i32> %t0, <i32 1, i32 1>

test/Transforms/InstCombine/vector-udiv.ll

@@ -22,17 +22,19 @@ define <4 x i32> @test_v4i32_const_pow2(<4 x i32> %a0) {
 ; X udiv C, where C >= signbit
 define <4 x i32> @test_v4i32_negconstsplat(<4 x i32> %a0) {
 ; CHECK-LABEL: @test_v4i32_negconstsplat(
-; CHECK-NEXT:    [[TMP1:%.*]] = udiv <4 x i32> [[A0:%.*]], <i32 -3, i32 -3, i32 -3, i32 -3>
-; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt <4 x i32> [[A0:%.*]], <i32 -4, i32 -4, i32 -4, i32 -4>
+; CHECK-NEXT:    [[TMP2:%.*]] = zext <4 x i1> [[TMP1]] to <4 x i32>
+; CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 ;
   %1 = udiv <4 x i32> %a0, <i32 -3, i32 -3, i32 -3, i32 -3>
   ret <4 x i32> %1
 }
 
 define <4 x i32> @test_v4i32_negconst(<4 x i32> %a0) {
 ; CHECK-LABEL: @test_v4i32_negconst(
-; CHECK-NEXT:    [[TMP1:%.*]] = udiv <4 x i32> [[A0:%.*]], <i32 -3, i32 -5, i32 -7, i32 -9>
-; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt <4 x i32> [[A0:%.*]], <i32 -4, i32 -6, i32 -8, i32 -10>
+; CHECK-NEXT:    [[TMP2:%.*]] = zext <4 x i1> [[TMP1]] to <4 x i32>
+; CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 ;
   %1 = udiv <4 x i32> %a0, <i32 -3, i32 -5, i32 -7, i32 -9>
   ret <4 x i32> %1