Skip to content
This repository was archived by the owner on Feb 5, 2019. It is now read-only.

Commit c5b286b

Browse files
filcabfilcab
committed
Rename X86insrtps to the proper instruction name.
Summary: The INSERTPS pattern fragment was called insrtps (mising 'e'), which would make it harder to grep for the patterns related to this instruction. Renaming it to use the proper instruction name. Reviewers: nadav CC: llvm-commits Differential Revision: http://reviews.llvm.org/D3443 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206779 91177308-0d34-0410-b5e6-96231b3b80d8
1 parent 51d1381 commit c5b286b

File tree

3 files changed

+15
-15
lines changed

3 files changed

+15
-15
lines changed

‎lib/Target/X86/X86InstrAVX512.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -209,12 +209,12 @@ def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
209209
def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
210210
(ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
211211
"vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
212-
[(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
212+
[(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
213213
EVEX_4V;
214214
def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
215215
(ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
216216
"vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
217-
[(set VR128X:$dst, (X86insrtps VR128X:$src1,
217+
[(set VR128X:$dst, (X86insertps VR128X:$src1,
218218
(v4f32 (scalar_to_vector (loadf32 addr:$src2))),
219219
imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
220220

‎lib/Target/X86/X86InstrFragmentsSIMD.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -81,7 +81,7 @@ def X86pinsrb : SDNode<"X86ISD::PINSRB",
8181
def X86pinsrw : SDNode<"X86ISD::PINSRW",
8282
SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
8383
SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
84-
def X86insrtps : SDNode<"X86ISD::INSERTPS",
84+
def X86insertps : SDNode<"X86ISD::INSERTPS",
8585
SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
8686
SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
8787
def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",

‎lib/Target/X86/X86InstrSSE.td

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -3157,23 +3157,23 @@ let Predicates = [UseSSE2] in {
31573157

31583158
let Predicates = [UseSSE41] in {
31593159
// If the subtarget has SSE4.1 but not AVX, the vector insert
3160-
// instruction is lowered into a X86insrtps rather than a X86Movss.
3160+
// instruction is lowered into a X86insertps rather than a X86Movss.
31613161
// When selecting SSE scalar single-precision fp arithmetic instructions,
3162-
// make sure that we correctly match the X86insrtps.
3162+
// make sure that we correctly match the X86insertps.
31633163

3164-
def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3164+
def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
31653165
(fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
31663166
FR32:$src))), (iPTR 0))),
31673167
(ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3168-
def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3168+
def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
31693169
(fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
31703170
FR32:$src))), (iPTR 0))),
31713171
(SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3172-
def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3172+
def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
31733173
(fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
31743174
FR32:$src))), (iPTR 0))),
31753175
(MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3176-
def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3176+
def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
31773177
(fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
31783178
FR32:$src))), (iPTR 0))),
31793179
(DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
@@ -3199,19 +3199,19 @@ let Predicates = [HasAVX] in {
31993199
(f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
32003200
FR64:$src))))),
32013201
(VDIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3202-
def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3202+
def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
32033203
(fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
32043204
FR32:$src))), (iPTR 0))),
32053205
(VADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3206-
def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3206+
def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
32073207
(fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
32083208
FR32:$src))), (iPTR 0))),
32093209
(VSUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3210-
def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3210+
def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
32113211
(fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
32123212
FR32:$src))), (iPTR 0))),
32133213
(VMULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3214-
def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3214+
def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
32153215
(fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
32163216
FR32:$src))), (iPTR 0))),
32173217
(VDIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
@@ -6528,7 +6528,7 @@ multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
65286528
!strconcat(asm,
65296529
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
65306530
[(set VR128:$dst,
6531-
(X86insrtps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
6531+
(X86insertps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
65326532
Sched<[WriteFShuffle]>;
65336533
def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
65346534
(ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
@@ -6537,7 +6537,7 @@ multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
65376537
!strconcat(asm,
65386538
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
65396539
[(set VR128:$dst,
6540-
(X86insrtps VR128:$src1,
6540+
(X86insertps VR128:$src1,
65416541
(v4f32 (scalar_to_vector (loadf32 addr:$src2))),
65426542
imm:$src3))], itins.rm>,
65436543
Sched<[WriteFShuffleLd, ReadAfterLd]>;

0 commit comments

Comments
 (0)