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[AArch64][SVE] Asm: Support for predicated FP operations.
This patch adds support for the following floating point instructions: FABD (absolute difference) FADD (addition) FSUB (subtract) FSUBR (subtract reverse form) FDIV (divide) FDIVR (divide reverse form) FMAX (maximum) FMAXNM (maximum number) FMIN (minimum) FMINNM (minimum number) FSCALE (adjust exponent) FMULX (multiply extended) All operations are predicated and binary form, e.g. fadd z0.h, p0/m, z0.h, z1.h ^___________^ (tied) Supporting 16, 32 and 64-bit FP elements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337259 91177308-0d34-0410-b5e6-96231b3b80d8
1 parent ead04a9 commit ca47e5e

28 files changed

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lines changed

‎lib/Target/AArch64/AArch64SVEInstrInfo.td

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -85,6 +85,20 @@ let Predicates = [HasSVE] in {
8585
defm FMUL_ZPmI : sve_fp_2op_i_p_zds<0b010, "fmul", sve_fpimm_half_two>;
8686
defm FMAX_ZPmI : sve_fp_2op_i_p_zds<0b110, "fmax", sve_fpimm_zero_one>;
8787

88+
defm FADD_ZPmZ : sve_fp_2op_p_zds<0b0000, "fadd">;
89+
defm FSUB_ZPmZ : sve_fp_2op_p_zds<0b0001, "fsub">;
90+
defm FMUL_ZPmZ : sve_fp_2op_p_zds<0b0010, "fmul">;
91+
defm FSUBR_ZPmZ : sve_fp_2op_p_zds<0b0011, "fsubr">;
92+
defm FMAXNM_ZPmZ : sve_fp_2op_p_zds<0b0100, "fmaxnm">;
93+
defm FMINNM_ZPmZ : sve_fp_2op_p_zds<0b0101, "fminnm">;
94+
defm FMAX_ZPmZ : sve_fp_2op_p_zds<0b0110, "fmax">;
95+
defm FMIN_ZPmZ : sve_fp_2op_p_zds<0b0111, "fmin">;
96+
defm FABD_ZPmZ : sve_fp_2op_p_zds<0b1000, "fabd">;
97+
defm FSCALE_ZPmZ : sve_fp_2op_p_zds<0b1001, "fscale">;
98+
defm FMULX_ZPmZ : sve_fp_2op_p_zds<0b1010, "fmulx">;
99+
defm FDIVR_ZPmZ : sve_fp_2op_p_zds<0b1100, "fdivr">;
100+
defm FDIV_ZPmZ : sve_fp_2op_p_zds<0b1101, "fdiv">;
101+
88102
defm FCADD_ZPmZ : sve_fp_fcadd<"fcadd">;
89103
defm FCMLA_ZPmZZ : sve_fp_fcmla<"fcmla">;
90104

‎lib/Target/AArch64/SVEInstrFormats.td

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -958,6 +958,34 @@ multiclass sve_fp_2op_i_p_zds<bits<3> opc, string asm, Operand imm_ty> {
958958
def _D : sve_fp_2op_i_p_zds<0b11, opc, asm, ZPR64, imm_ty>;
959959
}
960960

961+
class sve_fp_2op_p_zds<bits<2> sz, bits<4> opc, string asm,
962+
ZPRRegOp zprty>
963+
: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
964+
asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm",
965+
"",
966+
[]>, Sched<[]> {
967+
bits<3> Pg;
968+
bits<5> Zdn;
969+
bits<5> Zm;
970+
let Inst{31-24} = 0b01100101;
971+
let Inst{23-22} = sz;
972+
let Inst{21-20} = 0b00;
973+
let Inst{19-16} = opc;
974+
let Inst{15-13} = 0b100;
975+
let Inst{12-10} = Pg;
976+
let Inst{9-5} = Zm;
977+
let Inst{4-0} = Zdn;
978+
979+
let Constraints = "$Zdn = $_Zdn";
980+
}
981+
982+
multiclass sve_fp_2op_p_zds<bits<4> opc, string asm> {
983+
def _H : sve_fp_2op_p_zds<0b01, opc, asm, ZPR16>;
984+
def _S : sve_fp_2op_p_zds<0b10, opc, asm, ZPR32>;
985+
def _D : sve_fp_2op_p_zds<0b11, opc, asm, ZPR64>;
986+
}
987+
988+
961989
//===----------------------------------------------------------------------===//
962990
// SVE Floating Point Multiply - Indexed Group
963991
//===----------------------------------------------------------------------===//

‎test/MC/AArch64/SVE/fabd-diagnostics.s

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@@ -0,0 +1,33 @@
1+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
2+
3+
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// ------------------------------------------------------------------------- //
5+
// Tied operands must match
6+
7+
fabd z0.h, p7/m, z1.h, z31.h
8+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
9+
// CHECK-NEXT: fabd z0.h, p7/m, z1.h, z31.h
10+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
11+
12+
13+
// ------------------------------------------------------------------------- //
14+
// Invalid element widths.
15+
16+
fabd z0.b, p7/m, z0.b, z31.b
17+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
18+
// CHECK-NEXT: fabd z0.b, p7/m, z0.b, z31.b
19+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
20+
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fabd z0.h, p7/m, z0.h, z31.s
22+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
23+
// CHECK-NEXT: fabd z0.h, p7/m, z0.h, z31.s
24+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
25+
26+
27+
// ------------------------------------------------------------------------- //
28+
// Invalid predicate
29+
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fabd z0.h, p8/m, z0.h, z31.h
31+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
32+
// CHECK-NEXT: fabd z0.h, p8/m, z0.h, z31.h
33+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎test/MC/AArch64/SVE/fabd.s

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
4+
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
5+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
6+
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
7+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8+
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
9+
10+
fabd z0.h, p7/m, z0.h, z31.h
11+
// CHECK-INST: fabd z0.h, p7/m, z0.h, z31.h
12+
// CHECK-ENCODING: [0xe0,0x9f,0x48,0x65]
13+
// CHECK-ERROR: instruction requires: sve
14+
// CHECK-UNKNOWN: e0 9f 48 65 <unknown>
15+
16+
fabd z0.s, p7/m, z0.s, z31.s
17+
// CHECK-INST: fabd z0.s, p7/m, z0.s, z31.s
18+
// CHECK-ENCODING: [0xe0,0x9f,0x88,0x65]
19+
// CHECK-ERROR: instruction requires: sve
20+
// CHECK-UNKNOWN: e0 9f 88 65 <unknown>
21+
22+
fabd z0.d, p7/m, z0.d, z31.d
23+
// CHECK-INST: fabd z0.d, p7/m, z0.d, z31.d
24+
// CHECK-ENCODING: [0xe0,0x9f,0xc8,0x65]
25+
// CHECK-ERROR: instruction requires: sve
26+
// CHECK-UNKNOWN: e0 9f c8 65 <unknown>

‎test/MC/AArch64/SVE/fadd-diagnostics.s

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,3 +27,35 @@ fadd z0.h, p0/m, z0.h, #0.9999999999999999999999999
2727
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid floating point constant, expected 0.5 or 1.0.
2828
// CHECK-NEXT: fadd z0.h, p0/m, z0.h, #0.9999999999999999999999999
2929
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
30+
31+
32+
// ------------------------------------------------------------------------- //
33+
// Tied operands must match
34+
35+
fadd z0.h, p7/m, z1.h, z31.h
36+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
37+
// CHECK-NEXT: fadd z0.h, p7/m, z1.h, z31.h
38+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
39+
40+
41+
// ------------------------------------------------------------------------- //
42+
// Invalid element widths.
43+
44+
fadd z0.b, p7/m, z0.b, z31.b
45+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
46+
// CHECK-NEXT: fadd z0.b, p7/m, z0.b, z31.b
47+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
48+
49+
fadd z0.h, p7/m, z0.h, z31.s
50+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
51+
// CHECK-NEXT: fadd z0.h, p7/m, z0.h, z31.s
52+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
53+
54+
55+
// ------------------------------------------------------------------------- //
56+
// Invalid predicate
57+
58+
fadd z0.h, p8/m, z0.h, z31.h
59+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
60+
// CHECK-NEXT: fadd z0.h, p8/m, z0.h, z31.h
61+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎test/MC/AArch64/SVE/fadd.s

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -54,3 +54,21 @@ fadd z31.d, p7/m, z31.d, #1.0
5454
// CHECK-ENCODING: [0x3f,0x9c,0xd8,0x65]
5555
// CHECK-ERROR: instruction requires: sve
5656
// CHECK-UNKNOWN: 3f 9c d8 65 <unknown>
57+
58+
fadd z0.h, p7/m, z0.h, z31.h
59+
// CHECK-INST: fadd z0.h, p7/m, z0.h, z31.h
60+
// CHECK-ENCODING: [0xe0,0x9f,0x40,0x65]
61+
// CHECK-ERROR: instruction requires: sve
62+
// CHECK-UNKNOWN: e0 9f 40 65 <unknown>
63+
64+
fadd z0.s, p7/m, z0.s, z31.s
65+
// CHECK-INST: fadd z0.s, p7/m, z0.s, z31.s
66+
// CHECK-ENCODING: [0xe0,0x9f,0x80,0x65]
67+
// CHECK-ERROR: instruction requires: sve
68+
// CHECK-UNKNOWN: e0 9f 80 65 <unknown>
69+
70+
fadd z0.d, p7/m, z0.d, z31.d
71+
// CHECK-INST: fadd z0.d, p7/m, z0.d, z31.d
72+
// CHECK-ENCODING: [0xe0,0x9f,0xc0,0x65]
73+
// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 9f c0 65 <unknown>

‎test/MC/AArch64/SVE/fdiv-diagnostics.s

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,33 @@
1+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
2+
3+
4+
// ------------------------------------------------------------------------- //
5+
// Tied operands must match
6+
7+
fdiv z0.h, p7/m, z1.h, z31.h
8+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
9+
// CHECK-NEXT: fdiv z0.h, p7/m, z1.h, z31.h
10+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
11+
12+
13+
// ------------------------------------------------------------------------- //
14+
// Invalid element widths.
15+
16+
fdiv z0.b, p7/m, z0.b, z31.b
17+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
18+
// CHECK-NEXT: fdiv z0.b, p7/m, z0.b, z31.b
19+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
20+
21+
fdiv z0.h, p7/m, z0.h, z31.s
22+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
23+
// CHECK-NEXT: fdiv z0.h, p7/m, z0.h, z31.s
24+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
25+
26+
27+
// ------------------------------------------------------------------------- //
28+
// Invalid predicate
29+
30+
fdiv z0.h, p8/m, z0.h, z31.h
31+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
32+
// CHECK-NEXT: fdiv z0.h, p8/m, z0.h, z31.h
33+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎test/MC/AArch64/SVE/fdiv.s

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
4+
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
5+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
6+
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
7+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8+
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
9+
10+
fdiv z0.h, p7/m, z0.h, z31.h
11+
// CHECK-INST: fdiv z0.h, p7/m, z0.h, z31.h
12+
// CHECK-ENCODING: [0xe0,0x9f,0x4d,0x65]
13+
// CHECK-ERROR: instruction requires: sve
14+
// CHECK-UNKNOWN: e0 9f 4d 65 <unknown>
15+
16+
fdiv z0.s, p7/m, z0.s, z31.s
17+
// CHECK-INST: fdiv z0.s, p7/m, z0.s, z31.s
18+
// CHECK-ENCODING: [0xe0,0x9f,0x8d,0x65]
19+
// CHECK-ERROR: instruction requires: sve
20+
// CHECK-UNKNOWN: e0 9f 8d 65 <unknown>
21+
22+
fdiv z0.d, p7/m, z0.d, z31.d
23+
// CHECK-INST: fdiv z0.d, p7/m, z0.d, z31.d
24+
// CHECK-ENCODING: [0xe0,0x9f,0xcd,0x65]
25+
// CHECK-ERROR: instruction requires: sve
26+
// CHECK-UNKNOWN: e0 9f cd 65 <unknown>

‎test/MC/AArch64/SVE/fdivr-diagnostics.s

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,33 @@
1+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
2+
3+
4+
// ------------------------------------------------------------------------- //
5+
// Tied operands must match
6+
7+
fdivr z0.h, p7/m, z1.h, z31.h
8+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
9+
// CHECK-NEXT: fdivr z0.h, p7/m, z1.h, z31.h
10+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
11+
12+
13+
// ------------------------------------------------------------------------- //
14+
// Invalid element widths.
15+
16+
fdivr z0.b, p7/m, z0.b, z31.b
17+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
18+
// CHECK-NEXT: fdivr z0.b, p7/m, z0.b, z31.b
19+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
20+
21+
fdivr z0.h, p7/m, z0.h, z31.s
22+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
23+
// CHECK-NEXT: fdivr z0.h, p7/m, z0.h, z31.s
24+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
25+
26+
27+
// ------------------------------------------------------------------------- //
28+
// Invalid predicate
29+
30+
fdivr z0.h, p8/m, z0.h, z31.h
31+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
32+
// CHECK-NEXT: fdivr z0.h, p8/m, z0.h, z31.h
33+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎test/MC/AArch64/SVE/fdivr.s

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
4+
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
5+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
6+
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
7+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8+
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
9+
10+
fdivr z0.h, p7/m, z0.h, z31.h
11+
// CHECK-INST: fdivr z0.h, p7/m, z0.h, z31.h
12+
// CHECK-ENCODING: [0xe0,0x9f,0x4c,0x65]
13+
// CHECK-ERROR: instruction requires: sve
14+
// CHECK-UNKNOWN: e0 9f 4c 65 <unknown>
15+
16+
fdivr z0.s, p7/m, z0.s, z31.s
17+
// CHECK-INST: fdivr z0.s, p7/m, z0.s, z31.s
18+
// CHECK-ENCODING: [0xe0,0x9f,0x8c,0x65]
19+
// CHECK-ERROR: instruction requires: sve
20+
// CHECK-UNKNOWN: e0 9f 8c 65 <unknown>
21+
22+
fdivr z0.d, p7/m, z0.d, z31.d
23+
// CHECK-INST: fdivr z0.d, p7/m, z0.d, z31.d
24+
// CHECK-ENCODING: [0xe0,0x9f,0xcc,0x65]
25+
// CHECK-ERROR: instruction requires: sve
26+
// CHECK-UNKNOWN: e0 9f cc 65 <unknown>

‎test/MC/AArch64/SVE/fmax-diagnostics.s

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,3 +28,34 @@ fmax z0.h, p0/m, z0.h, #0.9999999999999999999999999
2828
// CHECK-NEXT: fmax z0.h, p0/m, z0.h, #0.9999999999999999999999999
2929
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
3030

31+
32+
// ------------------------------------------------------------------------- //
33+
// Tied operands must match
34+
35+
fmax z0.h, p7/m, z1.h, z31.h
36+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
37+
// CHECK-NEXT: fmax z0.h, p7/m, z1.h, z31.h
38+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
39+
40+
41+
// ------------------------------------------------------------------------- //
42+
// Invalid element widths.
43+
44+
fmax z0.b, p7/m, z0.b, z31.b
45+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
46+
// CHECK-NEXT: fmax z0.b, p7/m, z0.b, z31.b
47+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
48+
49+
fmax z0.h, p7/m, z0.h, z31.s
50+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
51+
// CHECK-NEXT: fmax z0.h, p7/m, z0.h, z31.s
52+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
53+
54+
55+
// ------------------------------------------------------------------------- //
56+
// Invalid predicate
57+
58+
fmax z0.h, p8/m, z0.h, z31.h
59+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
60+
// CHECK-NEXT: fmax z0.h, p8/m, z0.h, z31.h
61+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎test/MC/AArch64/SVE/fmax.s

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -48,3 +48,21 @@ fmax z0.d, p0/m, z0.d, #0.0
4848
// CHECK-ENCODING: [0x00,0x80,0xde,0x65]
4949
// CHECK-ERROR: instruction requires: sve
5050
// CHECK-UNKNOWN: 00 80 de 65 <unknown>
51+
52+
fmax z0.h, p7/m, z0.h, z31.h
53+
// CHECK-INST: fmax z0.h, p7/m, z0.h, z31.h
54+
// CHECK-ENCODING: [0xe0,0x9f,0x46,0x65]
55+
// CHECK-ERROR: instruction requires: sve
56+
// CHECK-UNKNOWN: e0 9f 46 65 <unknown>
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fmax z0.s, p7/m, z0.s, z31.s
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// CHECK-INST: fmax z0.s, p7/m, z0.s, z31.s
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// CHECK-ENCODING: [0xe0,0x9f,0x86,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 9f 86 65 <unknown>
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fmax z0.d, p7/m, z0.d, z31.d
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// CHECK-INST: fmax z0.d, p7/m, z0.d, z31.d
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// CHECK-ENCODING: [0xe0,0x9f,0xc6,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 9f c6 65 <unknown>

‎test/MC/AArch64/SVE/fmaxnm-diagnostics.s

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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// ------------------------------------------------------------------------- //
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// Tied operands must match
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fmaxnm z0.h, p7/m, z1.h, z31.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
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// CHECK-NEXT: fmaxnm z0.h, p7/m, z1.h, z31.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid element widths.
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fmaxnm z0.b, p7/m, z0.b, z31.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: fmaxnm z0.b, p7/m, z0.b, z31.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fmaxnm z0.h, p7/m, z0.h, z31.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: fmaxnm z0.h, p7/m, z0.h, z31.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid predicate
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fmaxnm z0.h, p8/m, z0.h, z31.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
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// CHECK-NEXT: fmaxnm z0.h, p8/m, z0.h, z31.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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