Skip to content
This repository was archived by the owner on Feb 5, 2019. It is now read-only.

Commit d10901a

Browse files
zmodemzmodem
committed
Merging r309614:
------------------------------------------------------------------------ r309614 | kbelochapka | 2017-07-31 13:11:49 -0700 (Mon, 31 Jul 2017) | 7 lines [X86][MMX] Added custom lowering action for MMX SELECT (PR30418) Fix for pr30418 - error in backend: Cannot select: t17: x86mmx = select_cc t2, Constant:i64<0>, t7, t8, seteq:ch Differential Revision: https://reviews.llvm.org/D34661 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@310673 91177308-0d34-0410-b5e6-96231b3b80d8
1 parent 999f7b7 commit d10901a

File tree

2 files changed

+133
-0
lines changed

2 files changed

+133
-0
lines changed

‎lib/Target/X86/X86ISelLowering.cpp

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -419,6 +419,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
419419
setOperationAction(ISD::SELECT, VT, Custom);
420420
setOperationAction(ISD::SETCC, VT, Custom);
421421
}
422+
423+
// Custom action for SELECT MMX and expand action for SELECT_CC MMX
424+
setOperationAction(ISD::SELECT, MVT::x86mmx, Custom);
425+
setOperationAction(ISD::SELECT_CC, MVT::x86mmx, Expand);
426+
422427
setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
423428
// NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
424429
// SjLj exception handling but a light-weight setjmp/longjmp replacement to
@@ -30678,6 +30683,14 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
3067830683
return SDValue(N, 0);
3067930684
}
3068030685

30686+
// Custom action for SELECT MMX
30687+
if (VT == MVT::x86mmx) {
30688+
LHS = DAG.getBitcast(MVT::i64, LHS);
30689+
RHS = DAG.getBitcast(MVT::i64, RHS);
30690+
SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::i64, Cond, LHS, RHS);
30691+
return DAG.getBitcast(VT, newSelect);
30692+
}
30693+
3068130694
return SDValue();
3068230695
}
3068330696

‎test/CodeGen/X86/select-mmx.ll

Lines changed: 120 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,120 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+mmx < %s | FileCheck %s --check-prefix=X64
3+
; RUN: llc -mtriple=i686-unknown-unknown -mattr=+mmx < %s | FileCheck %s --check-prefix=I32
4+
5+
6+
; From source: clang -02
7+
;__m64 test47(int a)
8+
;{
9+
; __m64 x = (a)? (__m64)(7): (__m64)(0);
10+
; return __builtin_ia32_psllw(x, x);
11+
;}
12+
13+
define i64 @test47(i64 %arg) {
14+
;
15+
; X64-LABEL: test47:
16+
; X64: # BB#0:
17+
; X64-NEXT: xorl %eax, %eax
18+
; X64-NEXT: testq %rdi, %rdi
19+
; X64-NEXT: movl $7, %ecx
20+
; X64-NEXT: cmoveq %rcx, %rax
21+
; X64-NEXT: movd %rax, %mm0
22+
; X64-NEXT: psllw %mm0, %mm0
23+
; X64-NEXT: movd %mm0, %rax
24+
; X64-NEXT: retq
25+
;
26+
; I32-LABEL: test47:
27+
; I32: # BB#0:
28+
; I32-NEXT: pushl %ebp
29+
; I32-NEXT: .Lcfi0:
30+
; I32-NEXT: .cfi_def_cfa_offset 8
31+
; I32-NEXT: .Lcfi1:
32+
; I32-NEXT: .cfi_offset %ebp, -8
33+
; I32-NEXT: movl %esp, %ebp
34+
; I32-NEXT: .Lcfi2:
35+
; I32-NEXT: .cfi_def_cfa_register %ebp
36+
; I32-NEXT: andl $-8, %esp
37+
; I32-NEXT: subl $16, %esp
38+
; I32-NEXT: movl 8(%ebp), %eax
39+
; I32-NEXT: orl 12(%ebp), %eax
40+
; I32-NEXT: movl $7, %eax
41+
; I32-NEXT: je .LBB0_2
42+
; I32-NEXT: # BB#1:
43+
; I32-NEXT: xorl %eax, %eax
44+
; I32-NEXT: .LBB0_2:
45+
; I32-NEXT: movl %eax, {{[0-9]+}}(%esp)
46+
; I32-NEXT: movl $0, {{[0-9]+}}(%esp)
47+
; I32-NEXT: movq {{[0-9]+}}(%esp), %mm0
48+
; I32-NEXT: psllw %mm0, %mm0
49+
; I32-NEXT: movq %mm0, (%esp)
50+
; I32-NEXT: movl (%esp), %eax
51+
; I32-NEXT: movl {{[0-9]+}}(%esp), %edx
52+
; I32-NEXT: movl %ebp, %esp
53+
; I32-NEXT: popl %ebp
54+
; I32-NEXT: retl
55+
%cond = icmp eq i64 %arg, 0
56+
%slct = select i1 %cond, x86_mmx bitcast (i64 7 to x86_mmx), x86_mmx bitcast (i64 0 to x86_mmx)
57+
%psll = tail call x86_mmx @llvm.x86.mmx.psll.w(x86_mmx %slct, x86_mmx %slct)
58+
%retc = bitcast x86_mmx %psll to i64
59+
ret i64 %retc
60+
}
61+
62+
63+
; From source: clang -O2
64+
;__m64 test49(int a, long long n, long long m)
65+
;{
66+
; __m64 x = (a)? (__m64)(n): (__m64)(m);
67+
; return __builtin_ia32_psllw(x, x);
68+
;}
69+
70+
define i64 @test49(i64 %arg, i64 %x, i64 %y) {
71+
;
72+
; X64-LABEL: test49:
73+
; X64: # BB#0:
74+
; X64-NEXT: testq %rdi, %rdi
75+
; X64-NEXT: cmovneq %rdx, %rsi
76+
; X64-NEXT: movd %rsi, %mm0
77+
; X64-NEXT: psllw %mm0, %mm0
78+
; X64-NEXT: movd %mm0, %rax
79+
; X64-NEXT: retq
80+
;
81+
; I32-LABEL: test49:
82+
; I32: # BB#0:
83+
; I32-NEXT: pushl %ebp
84+
; I32-NEXT: .Lcfi3:
85+
; I32-NEXT: .cfi_def_cfa_offset 8
86+
; I32-NEXT: .Lcfi4:
87+
; I32-NEXT: .cfi_offset %ebp, -8
88+
; I32-NEXT: movl %esp, %ebp
89+
; I32-NEXT: .Lcfi5:
90+
; I32-NEXT: .cfi_def_cfa_register %ebp
91+
; I32-NEXT: andl $-8, %esp
92+
; I32-NEXT: subl $8, %esp
93+
; I32-NEXT: movl 8(%ebp), %eax
94+
; I32-NEXT: orl 12(%ebp), %eax
95+
; I32-NEXT: je .LBB1_1
96+
; I32-NEXT: # BB#2:
97+
; I32-NEXT: leal 24(%ebp), %eax
98+
; I32-NEXT: jmp .LBB1_3
99+
; I32-NEXT: .LBB1_1:
100+
; I32-NEXT: leal 16(%ebp), %eax
101+
; I32-NEXT: .LBB1_3:
102+
; I32-NEXT: movq (%eax), %mm0
103+
; I32-NEXT: psllw %mm0, %mm0
104+
; I32-NEXT: movq %mm0, (%esp)
105+
; I32-NEXT: movl (%esp), %eax
106+
; I32-NEXT: movl {{[0-9]+}}(%esp), %edx
107+
; I32-NEXT: movl %ebp, %esp
108+
; I32-NEXT: popl %ebp
109+
; I32-NEXT: retl
110+
%cond = icmp eq i64 %arg, 0
111+
%xmmx = bitcast i64 %x to x86_mmx
112+
%ymmx = bitcast i64 %y to x86_mmx
113+
%slct = select i1 %cond, x86_mmx %xmmx, x86_mmx %ymmx
114+
%psll = tail call x86_mmx @llvm.x86.mmx.psll.w(x86_mmx %slct, x86_mmx %slct)
115+
%retc = bitcast x86_mmx %psll to i64
116+
ret i64 %retc
117+
}
118+
119+
declare x86_mmx @llvm.x86.mmx.psll.w(x86_mmx, x86_mmx)
120+

0 commit comments

Comments
 (0)