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Commit e05ab11

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[X86] Use MVT instead of EVT in some places. NFC
Prior to this the compiled code probably had extra checks for extended types that won't ever execute. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251682 91177308-0d34-0410-b5e6-96231b3b80d8
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lib/Target/X86/X86ISelLowering.cpp

Lines changed: 41 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -1825,40 +1825,43 @@ EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
18251825
if (!VT.isVector())
18261826
return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
18271827

1828-
const unsigned NumElts = VT.getVectorNumElements();
1829-
const EVT EltVT = VT.getVectorElementType();
1830-
if (VT.is512BitVector()) {
1831-
if (Subtarget->hasAVX512())
1832-
if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1833-
EltVT == MVT::f32 || EltVT == MVT::f64)
1834-
switch(NumElts) {
1835-
case 8: return MVT::v8i1;
1836-
case 16: return MVT::v16i1;
1837-
}
1838-
if (Subtarget->hasBWI())
1839-
if (EltVT == MVT::i8 || EltVT == MVT::i16)
1840-
switch(NumElts) {
1841-
case 32: return MVT::v32i1;
1842-
case 64: return MVT::v64i1;
1843-
}
1844-
}
1828+
if (VT.isSimple()) {
1829+
MVT VVT = VT.getSimpleVT();
1830+
const unsigned NumElts = VVT.getVectorNumElements();
1831+
const MVT EltVT = VVT.getVectorElementType();
1832+
if (VVT.is512BitVector()) {
1833+
if (Subtarget->hasAVX512())
1834+
if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1835+
EltVT == MVT::f32 || EltVT == MVT::f64)
1836+
switch(NumElts) {
1837+
case 8: return MVT::v8i1;
1838+
case 16: return MVT::v16i1;
1839+
}
1840+
if (Subtarget->hasBWI())
1841+
if (EltVT == MVT::i8 || EltVT == MVT::i16)
1842+
switch(NumElts) {
1843+
case 32: return MVT::v32i1;
1844+
case 64: return MVT::v64i1;
1845+
}
1846+
}
18451847

1846-
if (VT.is256BitVector() || VT.is128BitVector()) {
1847-
if (Subtarget->hasVLX())
1848-
if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1849-
EltVT == MVT::f32 || EltVT == MVT::f64)
1850-
switch(NumElts) {
1851-
case 2: return MVT::v2i1;
1852-
case 4: return MVT::v4i1;
1853-
case 8: return MVT::v8i1;
1854-
}
1855-
if (Subtarget->hasBWI() && Subtarget->hasVLX())
1856-
if (EltVT == MVT::i8 || EltVT == MVT::i16)
1857-
switch(NumElts) {
1858-
case 8: return MVT::v8i1;
1859-
case 16: return MVT::v16i1;
1860-
case 32: return MVT::v32i1;
1861-
}
1848+
if (VVT.is256BitVector() || VVT.is128BitVector()) {
1849+
if (Subtarget->hasVLX())
1850+
if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1851+
EltVT == MVT::f32 || EltVT == MVT::f64)
1852+
switch(NumElts) {
1853+
case 2: return MVT::v2i1;
1854+
case 4: return MVT::v4i1;
1855+
case 8: return MVT::v8i1;
1856+
}
1857+
if (Subtarget->hasBWI() && Subtarget->hasVLX())
1858+
if (EltVT == MVT::i8 || EltVT == MVT::i16)
1859+
switch(NumElts) {
1860+
case 8: return MVT::v8i1;
1861+
case 16: return MVT::v16i1;
1862+
case 32: return MVT::v32i1;
1863+
}
1864+
}
18621865
}
18631866

18641867
return VT.changeVectorElementTypeToInteger();
@@ -14432,7 +14435,7 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
1443214435
// Since SSE has no unsigned integer comparisons, we need to flip the sign
1443314436
// bits of the inputs before performing those operations.
1443414437
if (FlipSigns) {
14435-
EVT EltVT = VT.getVectorElementType();
14438+
MVT EltVT = VT.getVectorElementType();
1443614439
SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
1443714440
VT);
1443814441
Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
@@ -18233,7 +18236,7 @@ static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
1823318236

1823418237
if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
1823518238
SDValue BaseShAmt;
18236-
EVT EltVT = VT.getVectorElementType();
18239+
MVT EltVT = VT.getVectorElementType();
1823718240

1823818241
if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
1823918242
// Check if this build_vector node is doing a splat.
@@ -19096,7 +19099,7 @@ static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
1909619099
SDValue InVec = Op->getOperand(0);
1909719100
SDLoc dl(Op);
1909819101
unsigned NumElts = SrcVT.getVectorNumElements();
19099-
EVT SVT = SrcVT.getVectorElementType();
19102+
MVT SVT = SrcVT.getVectorElementType();
1910019103

1910119104
// Widen the vector in input in the case of MVT::v2i32.
1910219105
// Example: from MVT::v2i32 to MVT::v4i32.
@@ -24404,7 +24407,8 @@ static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
2440424407
if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
2440524408
if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
2440624409
APInt ShiftAmt = AmtSplat->getAPIntValue();
24407-
unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
24410+
unsigned MaxAmount =
24411+
VT.getSimpleVT().getVectorElementType().getSizeInBits();
2440824412

2440924413
// SSE2/AVX2 logical shifts always return a vector of 0s
2441024414
// if the shift amount is bigger than or equal to

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