@@ -1825,40 +1825,43 @@ EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
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if (!VT.isVector())
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return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
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- const unsigned NumElts = VT.getVectorNumElements();
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- const EVT EltVT = VT.getVectorElementType();
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- if (VT.is512BitVector()) {
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- if (Subtarget->hasAVX512())
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- if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
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- EltVT == MVT::f32 || EltVT == MVT::f64)
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- switch(NumElts) {
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- case 8: return MVT::v8i1;
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- case 16: return MVT::v16i1;
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- }
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- if (Subtarget->hasBWI())
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- if (EltVT == MVT::i8 || EltVT == MVT::i16)
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- switch(NumElts) {
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- case 32: return MVT::v32i1;
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- case 64: return MVT::v64i1;
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- }
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- }
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+ if (VT.isSimple()) {
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+ MVT VVT = VT.getSimpleVT();
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+ const unsigned NumElts = VVT.getVectorNumElements();
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+ const MVT EltVT = VVT.getVectorElementType();
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+ if (VVT.is512BitVector()) {
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+ if (Subtarget->hasAVX512())
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+ if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
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+ EltVT == MVT::f32 || EltVT == MVT::f64)
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+ switch(NumElts) {
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+ case 8: return MVT::v8i1;
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+ case 16: return MVT::v16i1;
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+ }
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+ if (Subtarget->hasBWI())
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+ if (EltVT == MVT::i8 || EltVT == MVT::i16)
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+ switch(NumElts) {
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+ case 32: return MVT::v32i1;
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+ case 64: return MVT::v64i1;
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+ }
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+ }
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- if (VT.is256BitVector() || VT.is128BitVector()) {
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- if (Subtarget->hasVLX())
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- if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
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- EltVT == MVT::f32 || EltVT == MVT::f64)
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- switch(NumElts) {
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- case 2: return MVT::v2i1;
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- case 4: return MVT::v4i1;
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- case 8: return MVT::v8i1;
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- }
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- if (Subtarget->hasBWI() && Subtarget->hasVLX())
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- if (EltVT == MVT::i8 || EltVT == MVT::i16)
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- switch(NumElts) {
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- case 8: return MVT::v8i1;
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- case 16: return MVT::v16i1;
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- case 32: return MVT::v32i1;
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- }
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+ if (VVT.is256BitVector() || VVT.is128BitVector()) {
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+ if (Subtarget->hasVLX())
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+ if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
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+ EltVT == MVT::f32 || EltVT == MVT::f64)
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+ switch(NumElts) {
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+ case 2: return MVT::v2i1;
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+ case 4: return MVT::v4i1;
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+ case 8: return MVT::v8i1;
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+ }
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+ if (Subtarget->hasBWI() && Subtarget->hasVLX())
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+ if (EltVT == MVT::i8 || EltVT == MVT::i16)
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+ switch(NumElts) {
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+ case 8: return MVT::v8i1;
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+ case 16: return MVT::v16i1;
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+ case 32: return MVT::v32i1;
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+ }
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+ }
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}
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return VT.changeVectorElementTypeToInteger();
@@ -14432,7 +14435,7 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
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// Since SSE has no unsigned integer comparisons, we need to flip the sign
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// bits of the inputs before performing those operations.
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if (FlipSigns) {
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- EVT EltVT = VT.getVectorElementType();
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+ MVT EltVT = VT.getVectorElementType();
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SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
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VT);
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Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
@@ -18233,7 +18236,7 @@ static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
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if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
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SDValue BaseShAmt;
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- EVT EltVT = VT.getVectorElementType();
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+ MVT EltVT = VT.getVectorElementType();
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if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
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// Check if this build_vector node is doing a splat.
@@ -19096,7 +19099,7 @@ static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
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SDValue InVec = Op->getOperand(0);
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SDLoc dl(Op);
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unsigned NumElts = SrcVT.getVectorNumElements();
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- EVT SVT = SrcVT.getVectorElementType();
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+ MVT SVT = SrcVT.getVectorElementType();
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// Widen the vector in input in the case of MVT::v2i32.
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// Example: from MVT::v2i32 to MVT::v4i32.
@@ -24404,7 +24407,8 @@ static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
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if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
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if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
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APInt ShiftAmt = AmtSplat->getAPIntValue();
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- unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
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+ unsigned MaxAmount =
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+ VT.getSimpleVT().getVectorElementType().getSizeInBits();
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// SSE2/AVX2 logical shifts always return a vector of 0s
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// if the shift amount is bigger than or equal to
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