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GlobalISel: Remove dead code
Generic code should probably not introduce G_INSERT/G_EXTRACT. The mirror unpackRegs should also be removed, but AMDGPU still has a use remaining which needs to be fixed.
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llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h

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@@ -251,16 +251,6 @@ class CallLowering {
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SmallVectorImpl<ArgInfo> &SplitArgs,
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const DataLayout &DL, CallingConv::ID CallConv) const;
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/// Generate instructions for packing \p SrcRegs into one big register
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/// corresponding to the aggregate type \p PackedTy.
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///
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/// \param SrcRegs should contain one virtual register for each base type in
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/// \p PackedTy, as returned by computeValueLLTs.
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///
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/// \return The packed register.
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Register packRegs(ArrayRef<Register> SrcRegs, Type *PackedTy,
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MachineIRBuilder &MIRBuilder) const;
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/// Generate instructions for unpacking \p SrcReg into the \p DstRegs
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/// corresponding to the aggregate type \p PackedTy.
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///

llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

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@@ -224,31 +224,6 @@ void CallLowering::splitToValueTypes(const ArgInfo &OrigArg,
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SplitArgs.back().Flags[0].setInConsecutiveRegsLast();
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}
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Register CallLowering::packRegs(ArrayRef<Register> SrcRegs, Type *PackedTy,
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MachineIRBuilder &MIRBuilder) const {
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assert(SrcRegs.size() > 1 && "Nothing to pack");
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const DataLayout &DL = MIRBuilder.getMF().getDataLayout();
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MachineRegisterInfo *MRI = MIRBuilder.getMRI();
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LLT PackedLLT = getLLTForType(*PackedTy, DL);
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SmallVector<LLT, 8> LLTs;
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SmallVector<uint64_t, 8> Offsets;
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computeValueLLTs(DL, *PackedTy, LLTs, &Offsets);
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assert(LLTs.size() == SrcRegs.size() && "Regs / types mismatch");
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Register Dst = MRI->createGenericVirtualRegister(PackedLLT);
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MIRBuilder.buildUndef(Dst);
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for (unsigned i = 0; i < SrcRegs.size(); ++i) {
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Register NewDst = MRI->createGenericVirtualRegister(PackedLLT);
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MIRBuilder.buildInsert(NewDst, Dst, SrcRegs[i], Offsets[i]);
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Dst = NewDst;
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}
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return Dst;
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}
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void CallLowering::unpackRegs(ArrayRef<Register> DstRegs, Register SrcReg,
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Type *PackedTy,
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MachineIRBuilder &MIRBuilder) const {

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