---

yaml
---
r: 174275
b: refs/heads/snap-stage3
c: 7d4f358
h: refs/heads/master
i:
  174273: 8da9fd1
  174271: 2f5a9ea
v: v3

Author: huonw

[refs]

@@ -1,7 +1,7 @@
 ---
 refs/heads/master: a833337943300db1c310a4cf9c84b7b4ef4e9468
 refs/heads/snap-stage1: e33de59e47c5076a89eadeb38f4934f58a3618a6
-refs/heads/snap-stage3: 5edbe1f5ddab26a5a8ea75d447d5a37d8f7a3347
+refs/heads/snap-stage3: 7d4f358de7de97b443a97e1f18a16781d472bbda
 refs/heads/try: 08f6380a9f0b866796080094f44fe25ea5636547
 refs/tags/release-0.1: 1f5c5126e96c79d22cb7862f75304136e204f105
 refs/heads/dist-snap: ba4081a5a8573875fed17545846f6f6902c8ba8d

branches/snap-stage3/src/librustc_trans/trans/cabi_x86_64.rs

@@ -32,7 +32,7 @@ enum RegClass {
     SSEFv,
     SSEDs,
     SSEDv,
-    SSEInt,
+    SSEInt(/* bitwidth */ u64),
     /// Data that can appear in the upper half of an SSE register.
     SSEUp,
     X87,
@@ -57,7 +57,7 @@ impl TypeMethods for Type {
 impl RegClass {
     fn is_sse(&self) -> bool {
         match *self {
-            SSEFs | SSEFv | SSEDs | SSEDv => true,
+            SSEFs | SSEFv | SSEDs | SSEDv | SSEInt(_) => true,
             _ => false
         }
     }
@@ -254,7 +254,7 @@ fn classify_ty(ty: Type) -> Vec<RegClass> {
                 let elt = ty.element_type();
                 let eltsz = ty_size(elt);
                 let mut reg = match elt.kind() {
-                    Integer => SSEInt,
+                    Integer => SSEInt(elt.int_width()),
                     Float => SSEFv,
                     Double => SSEDv,
                     _ => panic!("classify: unhandled vector element type")
@@ -350,19 +350,19 @@ fn llreg_ty(ccx: &CrateContext, cls: &[RegClass]) -> Type {
             Int => {
                 tys.push(Type::i64(ccx));
             }
-            SSEFv | SSEDv | SSEInt => {
+            SSEFv | SSEDv | SSEInt(_) => {
                 let (elts_per_word, elt_ty) = match cls[i] {
                     SSEFv => (2, Type::f32(ccx)),
                     SSEDv => (1, Type::f64(ccx)),
-                    // FIXME: need to handle the element types, since
-                    // C doesn't distinguish between the contained
-                    // types of the vector at all; normalise to u8,
-                    // maybe?
-                    SSEInt => panic!("llregtype: SSEInt not yet supported"),
+                    SSEInt(bits) => {
+                        assert!(bits == 8 || bits == 16 || bits == 32 || bits == 64,
+                                "llreg_ty: unsupported SSEInt width {}", bits);
+                        (64 / bits, Type::ix(ccx, bits))
+                    }
                     _ => unreachable!(),
                 };
                 let vec_len = llvec_len(&cls[(i + 1u)..]);
-                let vec_ty = Type::vector(&elt_ty, (vec_len * elts_per_word) as u64);
+                let vec_ty = Type::vector(&elt_ty, vec_len as u64 * elts_per_word);
                 tys.push(vec_ty);
                 i += vec_len;
                 continue;