Skip to content

Commit 33bc396

Browse files
committed
Make FalseEdges always have two targets
We never have more than one imaginary target, so we have no reason for a `Vec`
1 parent 55cee44 commit 33bc396

File tree

7 files changed

+21
-32
lines changed

7 files changed

+21
-32
lines changed

src/librustc/mir/mod.rs

Lines changed: 9 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1196,9 +1196,9 @@ pub enum TerminatorKind<'tcx> {
11961196
FalseEdges {
11971197
/// The target normal control flow will take
11981198
real_target: BasicBlock,
1199-
/// The list of blocks control flow could conceptually take, but won't
1199+
/// A block control flow could conceptually take, but won't
12001200
/// in practice
1201-
imaginary_targets: Vec<BasicBlock>,
1201+
imaginary_target: BasicBlock,
12021202
},
12031203
/// A terminator for blocks that only take one path in reality, but where we
12041204
/// reserve the right to unwind in borrowck, even if it won't happen in practice.
@@ -1335,8 +1335,8 @@ impl<'tcx> TerminatorKind<'tcx> {
13351335
SwitchInt { ref targets, .. } => None.into_iter().chain(&targets[..]),
13361336
FalseEdges {
13371337
ref real_target,
1338-
ref imaginary_targets,
1339-
} => Some(real_target).into_iter().chain(&imaginary_targets[..]),
1338+
ref imaginary_target,
1339+
} => Some(real_target).into_iter().chain(slice::from_ref(imaginary_target)),
13401340
}
13411341
}
13421342

@@ -1422,10 +1422,10 @@ impl<'tcx> TerminatorKind<'tcx> {
14221422
} => None.into_iter().chain(&mut targets[..]),
14231423
FalseEdges {
14241424
ref mut real_target,
1425-
ref mut imaginary_targets,
1425+
ref mut imaginary_target,
14261426
} => Some(real_target)
14271427
.into_iter()
1428-
.chain(&mut imaginary_targets[..]),
1428+
.chain(slice::from_mut(imaginary_target)),
14291429
}
14301430
}
14311431

@@ -1722,12 +1722,9 @@ impl<'tcx> TerminatorKind<'tcx> {
17221722
Assert { cleanup: None, .. } => vec!["".into()],
17231723
Assert { .. } => vec!["success".into(), "unwind".into()],
17241724
FalseEdges {
1725-
ref imaginary_targets,
17261725
..
17271726
} => {
1728-
let mut l = vec!["real".into()];
1729-
l.resize(imaginary_targets.len() + 1, "imaginary".into());
1730-
l
1727+
vec!["real".into(), "imaginary".into()]
17311728
}
17321729
FalseUnwind {
17331730
unwind: Some(_), ..
@@ -3356,10 +3353,10 @@ impl<'tcx> TypeFoldable<'tcx> for Terminator<'tcx> {
33563353
Unreachable => Unreachable,
33573354
FalseEdges {
33583355
real_target,
3359-
ref imaginary_targets,
3356+
imaginary_target,
33603357
} => FalseEdges {
33613358
real_target,
3362-
imaginary_targets: imaginary_targets.clone(),
3359+
imaginary_target,
33633360
},
33643361
FalseUnwind {
33653362
real_target,

src/librustc_mir/borrow_check/mod.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -780,7 +780,7 @@ impl<'cx, 'gcx, 'tcx> DataflowResultsConsumer<'cx, 'tcx> for MirBorrowckCtxt<'cx
780780
| TerminatorKind::Unreachable
781781
| TerminatorKind::FalseEdges {
782782
real_target: _,
783-
imaginary_targets: _,
783+
imaginary_target: _,
784784
}
785785
| TerminatorKind::FalseUnwind {
786786
real_target: _,

src/librustc_mir/borrow_check/nll/invalidation.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -244,7 +244,7 @@ impl<'cx, 'tcx, 'gcx> Visitor<'tcx> for InvalidationGenerator<'cx, 'tcx, 'gcx> {
244244
| TerminatorKind::Unreachable
245245
| TerminatorKind::FalseEdges {
246246
real_target: _,
247-
imaginary_targets: _,
247+
imaginary_target: _,
248248
}
249249
| TerminatorKind::FalseUnwind {
250250
real_target: _,

src/librustc_mir/borrow_check/nll/type_check/mod.rs

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1792,12 +1792,10 @@ impl<'a, 'gcx, 'tcx> TypeChecker<'a, 'gcx, 'tcx> {
17921792
}
17931793
TerminatorKind::FalseEdges {
17941794
real_target,
1795-
ref imaginary_targets,
1795+
imaginary_target,
17961796
} => {
17971797
self.assert_iscleanup(body, block_data, real_target, is_cleanup);
1798-
for target in imaginary_targets {
1799-
self.assert_iscleanup(body, block_data, *target, is_cleanup);
1800-
}
1798+
self.assert_iscleanup(body, block_data, imaginary_target, is_cleanup);
18011799
}
18021800
TerminatorKind::FalseUnwind {
18031801
real_target,

src/librustc_mir/build/matches/mod.rs

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -961,9 +961,7 @@ impl<'a, 'gcx, 'tcx> Builder<'a, 'gcx, 'tcx> {
961961
source_info,
962962
TerminatorKind::FalseEdges {
963963
real_target: second_candidate.pre_binding_block,
964-
imaginary_targets: vec![
965-
first_candidate.next_candidate_pre_binding_block
966-
],
964+
imaginary_target: first_candidate.next_candidate_pre_binding_block,
967965
}
968966
)
969967
} else {
@@ -984,7 +982,7 @@ impl<'a, 'gcx, 'tcx> Builder<'a, 'gcx, 'tcx> {
984982
source_info,
985983
TerminatorKind::FalseEdges {
986984
real_target: unreachable,
987-
imaginary_targets: vec![candidate.next_candidate_pre_binding_block],
985+
imaginary_targets: candidate.next_candidate_pre_binding_block,
988986
}
989987
);
990988
self.cfg.terminate(unreachable, source_info, TerminatorKind::Unreachable);
@@ -1001,7 +999,7 @@ impl<'a, 'gcx, 'tcx> Builder<'a, 'gcx, 'tcx> {
1001999
source_info,
10021000
TerminatorKind::FalseEdges {
10031001
real_target: block,
1004-
imaginary_targets: vec![last_candidate.next_candidate_pre_binding_block]
1002+
imaginary_target: last_candidate.next_candidate_pre_binding_block,
10051003
}
10061004
);
10071005
Some(block)
@@ -1330,7 +1328,7 @@ impl<'a, 'gcx, 'tcx> Builder<'a, 'gcx, 'tcx> {
13301328
candidate_source_info,
13311329
TerminatorKind::FalseEdges {
13321330
real_target: block,
1333-
imaginary_targets: vec![candidate.next_candidate_pre_binding_block],
1331+
imaginary_target: candidate.next_candidate_pre_binding_block,
13341332
},
13351333
);
13361334
self.ascribe_types(block, &candidate.ascriptions);

src/librustc_mir/dataflow/mod.rs

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -802,11 +802,9 @@ impl<'a, 'tcx: 'a, D> DataflowAnalysis<'a, 'tcx, D> where D: BitDenotation<'tcx>
802802
self.propagate_bits_into_entry_set_for(in_out, dest_bb, dirty_list);
803803
}
804804
}
805-
mir::TerminatorKind::FalseEdges { real_target, ref imaginary_targets } => {
805+
mir::TerminatorKind::FalseEdges { real_target, imaginary_target } => {
806806
self.propagate_bits_into_entry_set_for(in_out, real_target, dirty_list);
807-
for target in imaginary_targets {
808-
self.propagate_bits_into_entry_set_for(in_out, *target, dirty_list);
809-
}
807+
self.propagate_bits_into_entry_set_for(in_out, imaginary_target, dirty_list);
810808
}
811809
mir::TerminatorKind::FalseUnwind { real_target, unwind } => {
812810
self.propagate_bits_into_entry_set_for(in_out, real_target, dirty_list);

src/librustc_mir/transform/inline.rs

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -791,11 +791,9 @@ impl<'a, 'tcx> MutVisitor<'tcx> for Integrator<'a, 'tcx> {
791791
}
792792
TerminatorKind::Abort => { }
793793
TerminatorKind::Unreachable => { }
794-
TerminatorKind::FalseEdges { ref mut real_target, ref mut imaginary_targets } => {
794+
TerminatorKind::FalseEdges { ref mut real_target, ref mut imaginary_target } => {
795795
*real_target = self.update_target(*real_target);
796-
for target in imaginary_targets {
797-
*target = self.update_target(*target);
798-
}
796+
*imaginary_target = self.update_target(*imaginary_target);
799797
}
800798
TerminatorKind::FalseUnwind { real_target: _ , unwind: _ } =>
801799
// see the ordering of passes in the optimized_mir query.

0 commit comments

Comments
 (0)