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yaml --- r: 132525 b: refs/heads/dist-snap c: bf420e5 h: refs/heads/master i: 132523: da4446e v: v3
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[refs]

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ refs/heads/try: 457a3c991d79b971be07fce75f9d0c12848fb37c
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refs/tags/release-0.1: 1f5c5126e96c79d22cb7862f75304136e204f105
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refs/heads/ndm: f3868061cd7988080c30d6d5bf352a5a5fe2460b
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refs/heads/try2: 147ecfdd8221e4a4d4e090486829a06da1e0ca3c
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refs/heads/dist-snap: 862ba430c5bc1ba9e47644d2a75a6091842c53d0
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refs/heads/dist-snap: bf420e58c2f88c8f37f83aaf947e7abba1cd7f79
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refs/tags/release-0.2: c870d2dffb391e14efb05aa27898f1f6333a9596
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refs/tags/release-0.3: b5f0d0f648d9a6153664837026ba1be43d3e2503
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refs/heads/try3: 9387340aab40a73e8424c48fd42f0c521a4875c0

branches/dist-snap/src/libgreen/context.rs

Lines changed: 29 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,8 @@ use std::uint;
1313
use std::mem::transmute;
1414
use std::rt::stack;
1515
use std::raw;
16+
#[cfg(target_arch = "x86_64")]
17+
use std::simd;
1618

1719
// FIXME #7761: Registers is boxed so that it is 16-byte aligned, for storing
1820
// SSE regs. It would be marginally better not to do this. In C++ we
@@ -186,14 +188,30 @@ fn initialize_call_frame(regs: &mut Registers, fptr: InitFn, arg: uint,
186188
// windows requires saving more registers (both general and XMM), so the windows
187189
// register context must be larger.
188190
#[cfg(windows, target_arch = "x86_64")]
189-
type Registers = [uint, ..34];
191+
struct Registers {
192+
gpr:[uint, ..14],
193+
_xmm:[simd::u32x4, ..10]
194+
}
190195
#[cfg(not(windows), target_arch = "x86_64")]
191-
type Registers = [uint, ..22];
196+
struct Registers {
197+
gpr:[uint, ..10],
198+
_xmm:[simd::u32x4, ..6]
199+
}
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193201
#[cfg(windows, target_arch = "x86_64")]
194-
fn new_regs() -> Box<Registers> { box() ([0, .. 34]) }
202+
fn new_regs() -> Box<Registers> {
203+
box() Registers {
204+
gpr:[0,..14],
205+
_xmm:[simd::u32x4(0,0,0,0),..10]
206+
}
207+
}
195208
#[cfg(not(windows), target_arch = "x86_64")]
196-
fn new_regs() -> Box<Registers> { box() ([0, .. 22]) }
209+
fn new_regs() -> Box<Registers> {
210+
box() Registers {
211+
gpr:[0,..10],
212+
_xmm:[simd::u32x4(0,0,0,0),..6]
213+
}
214+
}
197215

198216
#[cfg(target_arch = "x86_64")]
199217
fn initialize_call_frame(regs: &mut Registers, fptr: InitFn, arg: uint,
@@ -222,20 +240,20 @@ fn initialize_call_frame(regs: &mut Registers, fptr: InitFn, arg: uint,
222240

223241
// These registers are frobbed by rust_bootstrap_green_task into the right
224242
// location so we can invoke the "real init function", `fptr`.
225-
regs[RUSTRT_R12] = arg as uint;
226-
regs[RUSTRT_R13] = procedure.code as uint;
227-
regs[RUSTRT_R14] = procedure.env as uint;
228-
regs[RUSTRT_R15] = fptr as uint;
243+
regs.gpr[RUSTRT_R12] = arg as uint;
244+
regs.gpr[RUSTRT_R13] = procedure.code as uint;
245+
regs.gpr[RUSTRT_R14] = procedure.env as uint;
246+
regs.gpr[RUSTRT_R15] = fptr as uint;
229247

230248
// These registers are picked up by the regular context switch paths. These
231249
// will put us in "mostly the right context" except for frobbing all the
232250
// arguments to the right place. We have the small trampoline code inside of
233251
// rust_bootstrap_green_task to do that.
234-
regs[RUSTRT_RSP] = sp as uint;
235-
regs[RUSTRT_IP] = rust_bootstrap_green_task as uint;
252+
regs.gpr[RUSTRT_RSP] = sp as uint;
253+
regs.gpr[RUSTRT_IP] = rust_bootstrap_green_task as uint;
236254

237255
// Last base pointer on the stack should be 0
238-
regs[RUSTRT_RBP] = 0;
256+
regs.gpr[RUSTRT_RBP] = 0;
239257
}
240258

241259
#[cfg(target_arch = "arm")]

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